PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F6410-I/PT
• Description: IC PIC MCU FLASH 8KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6410-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
27. Module: Timer1 (Asynchronous Counter)
TABLE 4:
EXAMPLE 5:
EXAMPLE 6:
DS80206F-page 10
Note:
When writing to the TMR1H register, under
specific conditions, it is possible that the TMR1L
register will miss a count while connected to the
external oscillator via the T1OSO and T1OSI pins.
When Timer1 is started, the circuitry looks for a
falling edge before a rising edge can increment the
counter. Writing to the TMR1H register is similar to
starting Timer1; therefore, the former logic stated
applies any time the TMR1H register is written. If the
TMR1H register is not completely written to during
the high pulse of the external clock, then the TMR1L
register will miss a count due to the circuit operation
stated previously. The high pulse of a 32.768 kHz
external clock crystal yields a 15.25 μs window for
the write to TMR1H to occur. The amount of
instructions that can be executed within this window
is frequency dependent, as shown in Table 4 below.
Date Codes that pertain to this issue:
ISR @ 0x0008
HIGHINT
ISR @ 0x0018
EXIT
BRA
BTFSC
BSF
RETFIE FAST
MOVFF
MOVFF
MOVFF
BTFSS
BRA
BSF
MOVFF
MOVFF
MOVFF
RETFIE
These instructions are required based on the function of the ISR. If the only code in the ISR is to reload
Timer1, then they are not required, but may be required if additional code is added.
16 MHz
20 MHz
40 MHz
FREQUENCY DEPENDENT INSTRUCTION EXECUTION AMOUNTS
1 MHz
2 MHz
4 MHz
8 MHz
F
OSC
HIGHINT
PIR1, TMR1IF
TMR1H, 7
STATUS, STATUS_TEMP
WREG, WREG_TEMP
BSR, BSR_TEMP
PIR1, TMR1IF
EXIT
TMR1H, 7
BSR_TEMP, BSR
WREG_TEMP, WREG
STATUS_TEMP, STATUS
PIC18 HIGH PRIORITY INTERRUPT SERVICE ROUTINE
PIC18 LOW PRIORITY INTERRUPT SERVICE ROUTINE
Total = 12-13 T
Total = 7-8 T
; (3-4Tcy), fixed interrupt latency
; (2Tcy), go to high priority interrupt routine
; (1Tcy), did a Timer1 overflow occur?
; (1Tcy) Yes, reload for a 1 second overflow
; (3-4Tcy), fixed interrupt latency
; (2Tcy), save STATUS register
; (2Tcy), save working register, refer to note 1
; (2Tcy), save BSR register, refer to note 1
; (2Tcy), did a Timer1 overflow occur?
; No
; (1Tcy) Yes, reload for a 1 second overflow
;restore BSR register, refer to note 1
;restore working register, refer to note 1
;restore STATUS register
CY
CY
(if Timer1 overflow occurred)
(if Timer1 overflow occurred)
T
CY
0.25
0.5
0.2
0.1
4
2
1
(μs)
Work around
Operating Conditions: F
from Sleep, Timer1 interrupt enabled, global
interrupts enabled.
The code excerpts in Example 5 and Example 6
show how the TMR1H register can be updated
while the external clock (32.768 kHz) is still on its
high pulse.
The importance of the code examples is that the
bold instructions are executed within the first
15.25 μs high pulse on the external clock after the
Timer1 overflow occurs. This will allow the TMR1L
register to increment correctly.
All engineering and production devices.
© 2007 Microchip Technology Inc.
T
CY
OSC
within 15.25 μs
15.25
76.25
152.5
≥ 4 MHz, no wake-ups
3.81
7.63
30.5
61