PIC18F45J50-I/PT Microchip Technology, PIC18F45J50-I/PT Datasheet - Page 549

• Manufacturer Part Number: PIC18F45J50-I/PT
• Description: IC PIC MCU FLASH 32K 2V 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3776Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Embedded Interface Type: EUSART, I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timing Diagrams and Specifications
TSTFSZ ........................................................................... 471
Two-Speed Start-up ................................................. 413, 427
Two-Word Instructions
© 2009 Microchip Technology Inc.
Timer1 Gate Count Enable Mode ............................ 200
Timer1 Gate Single Pulse Mode .............................. 203
Timer1 Gate Single Pulse/Toggle Combined Mode . 204
Timer1 Gate Toggle Mode ....................................... 202
Timer3 Gate Count Enable Mode ............................ 211
Timer3 Gate Single Pulse Mode .............................. 213
Timer3 Gate Single Pulse/Toggle Combined Mode . 214
Timer3 Gate Toggle Mode ....................................... 212
Transition for Entry to Idle Mode ................................ 46
Transition for Entry to SEC_RUN Mode .................... 43
Transition for Entry to Sleep Mode ............................ 45
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
Transition for Wake From Idle to Run Mode .............. 47
Transition for Wake From Sleep (HSPLL) ................. 45
Transition From RC_RUN Mode to PRI_RUN Mode . 44
Transition From SEC_RUN Mode to PRI_RUN Mode
Transition to RC_RUN Mode ..................................... 44
USB Signal ............................................................... 523
Write, 16-Bit Data, Demultiplexed Address .............. 183
Write, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit
Write, 16-Bit Multiplexed Data, Partially Multiplexed Ad-
Write, 8-Bit Data, Fully Multiplexed 16-Bit Address . 182
Write, 8-Bit Data, Partially Multiplexed Address ...... 181
Write, 8-Bit Data, Partially Multiplexed Address, Enable
Write, 8-Bit Data, Wait States Enabled, Partially Multi-
AC Characteristics
CLKO and I/O Requirements ................................... 507
Enhanced Capture/Compare/PWM Requirements .. 510
EUSARTx Synchronous Receive Requirements ..... 521
EUSARTx Synchronous Transmission Requirements ...
Example SPI Mode Requirements (Master Mode, CKE =
Example SPI Mode Requirements (Master Mode, CKE =
Example SPI Mode Requirements (Slave Mode, CKE =
Example SPI Slave Mode Requirements (CKE = 1) 516
External Clock Requirements .................................. 506
I
I
MSSPx I
MSSPx I
Parallel Master Port Read Requirements ................ 511
Parallel Master Port Write Requirements ................. 512
PLL Clock ................................................................. 506
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
Timer0 and Timer1 External Clock Requirements ... 509
USB Full-Speed Requirements ................................ 523
USB Low-Speed Requirements ............................... 523
Example Cases .......................................................... 77
2
2
C Bus Data Requirements (Slave Mode) .............. 518
C Bus Start/Stop Bits Requirements (Slave Mode) .....
427
(HSPLL) ............................................................. 43
Address ............................................................ 184
dress ................................................................ 184
Strobe .............................................................. 182
plexed Address ................................................ 181
Internal RC Accuracy ....................................... 506
521
0) ...................................................................... 513
1) ...................................................................... 514
0) ...................................................................... 515
517
er-up Timer and Brown-out Reset Requirements ..
508
2
2
C Bus Data Requirements ........................ 520
C Bus Start/Stop Bits Requirements ........ 519
PIC18F46J50 FAMILY
TXSTAx Register
U
Ultra Low-Power Wake-up ................................................. 54
Universal Serial Bus ........................................................ 351
USB Specifications .......................................................... 502
USB. See Universal Serial Bus.
V
Voltage Reference Specifications .................................... 500
Voltage Regulator (On-Chip) ........................................... 425
W
Watchdog Timer (WDT) ........................................... 413, 423
WCOL ...................................................... 305, 306, 307, 310
WCOL Status Flag ................................... 305, 306, 307, 310
BRGH Bit ................................................................. 321
Address Register (UADDR) ..................................... 359
Associated Registers ............................................... 375
Buffer Descriptor Table ............................................ 360
Buffer Descriptors .................................................... 360
Endpoint Control ...................................................... 358
External Pull-up Resistors ....................................... 356
Eye Pattern Test Enable .......................................... 356
Firmware and Drivers .............................................. 375
Frame Number Registers ........................................ 359
Internal Pull-up Resistors ........................................ 356
Internal Transceiver ................................................. 354
Interrupts ................................................................. 366
Oscillator Requirements .......................................... 375
Overview .......................................................... 351, 376
Ping-Pong Buffer Configuration ............................... 356
Power Modes ........................................................... 372
RAM ......................................................................... 359
Status and Control ................................................... 352
UFRMH:UFRML Registers ...................................... 359
Operation in Sleep Mode ......................................... 426
Associated Registers ............................................... 424
Control Register ....................................................... 423
During Oscillator Failure .......................................... 428
Programming Considerations .................................. 423
Address Validation ........................................... 363
Assignment in Different Buffering Modes ........ 365
BDnSTAT Register (CPU Mode) ..................... 361
BDnSTAT Register (SIE Mode) ....................... 363
Byte Count ....................................................... 363
Example .......................................................... 360
Memory Map .................................................... 364
Ownership ....................................................... 360
Ping-Pong Buffering ........................................ 364
Register Summary ........................................... 365
Status and Configuration ................................. 360
and USB Transactions ..................................... 366
Class Specifications and Drivers ..................... 377
Descriptors ...................................................... 377
Enumeration .................................................... 377
Frames ............................................................ 376
Layered Framework ......................................... 376
Power .............................................................. 376
Speed .............................................................. 377
Transfer Types ................................................ 376
Bus Power Only ............................................... 372
Dual Power with Self-Power Dominance ......... 372
Self-Power Only ............................................... 372
Transceiver Current Consumption ................... 373
Memory Map .................................................... 359
DS39931C-page 549