PIC12F635-I/MD Microchip Technology, PIC12F635-I/MD Datasheet - Page 94

• Manufacturer Part Number: PIC12F635-I/MD
• Description: IC PIC MCU FLASH 1KX14 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-I/MD

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNAC162057 - MPLAB ICD 2 HEADER 14DIPXLT08DFN - SOCKET TRANSITION ICE 8DFN
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC12F635/PIC16F636/639
9.1
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are
non-implemented and read as ‘0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
REGISTER 9-3:
DS41232D-page 92
bit 7
Legend:
S = Bit can only be set
R = Readable bit
-n = Value at POR
bit 7-4
bit 3
bit 2
bit 1
bit 0
U-0
—
EECON1 AND EECON2 Registers
Unimplemented: Read as ‘0’
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
0 = Does not initiate an EEPROM read
normal operation or BOR Reset)
be set, not cleared, in software.)
be set, not cleared, in software.)
U-0
—
EECON1: EEPROM CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-x
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit, clear it and rewrite the
location. The data and address will be cleared.
Therefore, the EEDAT and EEADR registers will need
to be re-initialized.
Interrupt flag, EEIF bit of the PIR1 register, is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
Note:
The EECON1, EEDAT and EEADR
registers should not be modified during a
data EEPROM write (WR bit = 1).
WREN
R/W-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0