PIC12F635-I/MD Microchip Technology, PIC12F635-I/MD Datasheet - Page 90

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PIC12F635-I/MD

Manufacturer Part Number
PIC12F635-I/MD
Description
IC PIC MCU FLASH 1KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets

Specifications of PIC12F635-I/MD

Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
128Byte
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNAC162057 - MPLAB ICD 2 HEADER 14DIPXLT08DFN - SOCKET TRANSITION ICE 8DFN
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

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PIC12F635/PIC16F636/639
8.1
To setup the PLVD for operation, the following steps
must be taken:
• Enable the module by setting the LVDEN bit of the
• Configure the trip point by setting the LVDL<2:0>
• Wait for the reference voltage to become stable.
• Clear the LVDIF bit of the PIRx register.
The LVDIF bit will be set when V
PLVD trip point. The LVDIF bit remains set until cleared
by software. Refer to Figure 8-2.
8.2
The PLVD trip point is selectable from one of eight
voltage levels. The LVDL bits of the LVDCON register
select the trip point. Refer to Register 8-1 for the
available PLVD trip points.
8.3
When V
edge detector will set the LVDIF bit. See Figure 8-2. An
interrupt will be generated if the following bits are also
set:
• GIE and PEIE bits of the INTCON register
• LVDIE bit of the PIEx register
The LVDIF bit must be cleared by software. An interrupt
can be generated from a simulated PLVD event when
the LVDIF bit is set by software.
DS41232D-page 88
LVDCON register.
bits of the LVDCON register.
Refer to Section 8.4 “Stable Reference
Indication”.
DD
PLVD Operation
Programmable Trip Point
Interrupt on Falling V
falls below the PLVD trip point, the falling
DD
DD
falls below the
8.4
When the PLVD module is enabled, the reference volt-
age must be allowed to stabilize before the PLVD will
provide a valid result. Refer to Electrical Section,
PLVD Characteristics for the stabilization time.
When the HFINTOSC is running, the IRVST bit of the
LVDCON register indicates the stability of the voltage
reference. The voltage reference is stable when the
IRVST bit is set.
8.5
To wake from Sleep, set the LVDIE bit of the PIEx
register and the PEIE bit of the INTCON register. When
the LVDIE and PEIE bits are set, the device will wake
from Sleep and execute the next instruction. If the GIE
bit is also set, the program will call the Interrupt Service
Routine upon completion of the first instruction after
waking from Sleep.
Stable Reference Indication
Operation During Sleep
© 2007 Microchip Technology Inc.

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