uja1069 NXP Semiconductors, uja1069 Datasheet
uja1069
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uja1069 Summary of contents
Page 1
... In failure situations the fail-safe SBC will maintain the microcontroller function for as long as possible, to provide full monitoring and software driven fall-back operation. The UJA1069 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures. Product data sheet ...
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... ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins 60 V short-circuit proof LIN-bus pin 7.8 mm HTSSOP24 package with low thermal resistance 11 mm HTSSOP32 package with low thermal resistance Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip © NXP B.V. 2007. All rights reserved ...
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... HTSSOP24 [1] UJA1069TW/5V0 is for the 5 V version; UJA1069TW/3V3 is for the 3.3 V version; UJA1069TW/3V0 is for the 3 V version. [2] UJA1069TW24/5V0 is for the 5 V version; UJA1069TW24/3V3 is for the 3.3 V version; UJA1069TW/3V0 is for the 3 V version. UJA1069_3 Product data sheet Description plastic thermal enhanced thin shrink small outline package; 32 leads; ...
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... SDO 12 (11) SCS 26 (18) RTLIN 25 (17) LIN 3 (2) TXDL 5 (4) RXDL 23 (15) GND The pin numbers in parenthesis are for the UJA1069TW24 version. Fig 1. Block diagram UJA1069_3 Product data sheet BAT MONITOR INH SBC FAIL-SAFE SYSTEM SPI LIN BAT42 Rev. 03 — 10 September 2007 ...
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... TEST 16 001aad676 1 n.c. TXDL RXDL RSTN 5 INTN 6 UJA1069TW24 SDI SDO 9 SCK 10 11 SCS TEST 12 001aad677 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip 32 BAT42 31 SENSE SYSINH 28 n.c. 27 BAT14 26 RTLIN 25 LIN 24 n.c. 23 GND 22 n.c. 21 n.c. 20 n.c. 19 n.c. 18 WAKE 17 ...
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... LIN bus line (LOW in dominant state LIN-bus termination resistor connection battery supply input 28 20 not connected 29 21 system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC converter) Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip © NXP B.V. 2007. All rights reserved ...
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... Fail-safe behavior 6.2 Fail-safe system controller The fail-safe system controller is the core of the UJA1069 and is supervised by a watchdog timer which is clocked directly by the dedicated on-chip oscillator. The system controller manages the register configuration and controls all internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. ...
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... WD(init) 16 Fail-safe mode V1: OFF SYSINH: HIGH/float LIN: off-line watchdog: OFF INH/LIMP: LOW RSTN: LOW EN: LOW Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip mode change via SPI Sleep mode I with reset option thH(V1) t RSTN(INT) V1: OFF SYSINH: HIGH/float LIN: off-line ...
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... RSTNL , to guarantee a discharged V1 before entering Start-up ret Section 6.5.1. Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip is observed. This reset time is RSTNL is set to the higher RSTNL © NXP B.V. 2007. All rights reserved. ...
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... possible to exit Standby mode without any system reset if required. UJA1069_3 Product data sheet , e.g. as result of a microcontroller wake-up from thH(V1) Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip . Entering Normal RSTN(INT) © NXP B.V. 2007. All rights reserved ...
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... Mode register, within the legal windows of the watchdog, using the UJA1069_3 Product data sheet . Otherwise a fail-safe system reset is forced and Start-up mode will be Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip © NXP B.V. 2007. All rights reserved ...
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... Illegal watchdog period coding; only ten different codes are valid • Illegal operating mode coding; only six different codes are valid UJA1069_3 Product data sheet Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip WD(init) © NXP B.V. 2007. All rights reserved ...
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... Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip , another reset is forced WD(init) Figure 4, Start-up mode and Restart trigger window 100 % latest possible trigger point ...
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... The Time-out mode can be used to provide cyclic period trigger range earliest possible trigger point trigger restarts period desired) Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip time-out latest possible trigger point trigger range new period while the watchdog is OFF, thH(V1) © ...
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... NXP Semiconductors 6.5 System reset The reset function of the UJA1069 offers two signals to deal with reset events: • RSTN; the global ECU system reset • EN; a fail-safe global enable signal 6.5.1 RSTN pin The system reset pin (RSTN bidirectional input / output. Pin RSTN is active LOW with selectable pulse length upon the following events ...
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... RSTNL RSTNL V RSTN t RSTNL RSTN externally forced LOW V RSTN t RSTNL RSTN externally forced LOW Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip V V under- power- voltage down spike RSTNL time t WD(init) time t WD(init) 001aad181 , the SBC RSTN(CLT) © ...
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... Connecting this pin in front of the polarity protection diode of the ECU provides an early warning if the battery becomes disconnected. 6.6.3 Voltage regulator V1 The UJA1069 has an independent voltage regulator supplied out of the BAT14 pin. Regulator V1 is intended to supply the microcontroller. The V1 voltage is continuously monitored to provide the system reset signal when undervoltage situations occur ...
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... Status register. This signals that the wake-up source via V3 supplied wake-up switches has been lost. 6.7 LIN transceiver The integrated LIN transceiver of the UJA1069 is a LIN 2.0 compliant transceiver. The transceiver has the following features: • SAE J2602 compliant and compatible with LIN revision 1.3 • ...
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... Restart or Fail-safe mode AND LMC = 1 Off-line mode transmitter: OFF power-on receiver: wake-up RXDL: wake-up status RTLIN: 75 A/OFF Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip SBC enters OR LMC = 0 SBC enters Fail-safe mode 001aad184 Figure 10. © NXP B.V. 2007. All rights reserved. ...
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... Active mode and receiver dominant OR Off-line mode Active mode and receiver recessive OR mode change to Active mode AND receiver recessive RTLIN = OFF power-on Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip t BUS(LIN) 001aad447 t LIN(dom)(det) RTLIN = 75 A supplied directly out of BAT42 ...
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... ILEN bit and ILC bit in the System Configuration register; see UJA1069_3 Product data sheet the transmitter is disabled BAT14 BAT42 ), the state of the LIN termination is changed according to Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip the LIN transmitter is TXDL(dom)(dis) (which is longer than LIN(dom)(det) Figure 11. Figure 12. © ...
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... SPI or V1 undervoltage) OR enter Fail-safe mode OR enter Restart mode OR enter Sleep mode INH/LIMP: floating ILEN = 0 power-on ILC = 1/0 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip INH/LIMP: LOW ILEN = 1 ILC = 0 state change via SPI 001aad178 ensures a BAT42 Figure © ...
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... Interrupt register. Without further INTN pin INTN stays HIGH, otherwise it will revert to LOW again. INTN 6.12.7. RSTN(INT) Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip button released signal remains LOW due to biasing (history) 001aac307 a system reset is performed. ...
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... UJA1069_3 Product data sheet Figure 14 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip LSB 01 LSB Figure 4 result in an immediate system reset Section 6.12.3 © NXP B.V. 2007. All rights reserved. X floating mce634 ...
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... Physical Layer Control Physical Layer Control register Feedback register General Purpose register 1 Physical Layer Control Feedback register Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip Table 3. The first two bits (A1 and Read Register Select (RRS) bit = 1 System Diagnosis register Interrupt register ...
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... EN output pin LOW 0 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip [1] [2] after system reset) the SBC will WD(init) © NXP B.V. 2007. All rights reserved. ...
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... OFF Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip Flash mode Sleep mode (ms) (ms) 20 160 40 320 80 640 160 1024 320 2048 640 3072 ...
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... Function 00 read System Status register 0 1 read System Status register without writing to Mode register 0 read System Status register and write to Mode register Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip Standby Flash mode Sleep mode mode (ms) (ms) (ms 560 ...
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... EN output activated (V1-related HIGH level) 0 pin EN output released (LOW level) 1 power-on reset; cleared after a successfully entered Normal mode 0 no power-on reset Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip exceeded WD(init) RSTN(INT) © NXP B.V. 2007. All rights reserved ...
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... Start-up mode and Restart mode a reset is performed instead of an interrupt 0 no interrupt forced; SPI access is ignored if the number of cycles does not equal 16 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip since last read access UV(VFI) since last read access; bit is set UV(VFI) © ...
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... Normal or Flash mode (unless LIN is in Active mode already) 0 LIN-bus event results in a reset in Standby mode; no interrupt in any other mode Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip …continued to guarantee an edge event at pin INTN © NXP B.V. 2007. All rights reserved. ...
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... LIN wake-up event has caused an interrupt 0 no interrupt Value Function 10 select System Configuration register 1 read the General Purpose Feedback register 0 0 read the System Configuration Feedback register Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip © NXP B.V. 2007. All rights reserved ...
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... Value Function 11 select Physical Layer Control register 1 read the General Purpose Feedback register 1 0 read the Physical Layer Control Feedback register Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip …continued long period; see Figure 13 w(CS) short period; see Figure 13 w(CS) © NXP B.V. 2007. All rights reserved. ...
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... Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip …continued © NXP B.V. 2007. All rights reserved ...
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... Not supported for the UJA1069TW/3V0 version. 6.12.11 General Purpose registers and General Purpose Feedback registers The UJA1069 offers two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) with no predefined bit definition. These registers can be used by the microcontroller for advanced system diagnosis or for storing critical system status information outside the microcontroller. After Power-up General Purpose register 0 will contain a ‘ ...
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... Power-on Start-up 0 (interrupt disabled) no change Power-on Start-up 0 (no interrupt) 0 (no interrupt) Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip …continued [1] [1] Restart 0000 or 0010 or 1100 or 1110 no change no change actual status actual status actual status ...
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... Power-on 0 (no) 00 (factor 1) 00 (90 %) Power-on 0 (Device ID) Mask version 000 1001 (UJA1069) no change Power-on 0000 0000 0000 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip Restart Fail-Safe 1 (long) 1 (long) no change no change no change no change ...
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... BAT42), thereby forcing a new power-on reset. UJA1069_3 Product data sheet is the only exception that results in entering Fail-safe mode (to protect the input voltage at pin TEST before the battery is th(TEST) Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 6.13.2 Forced normal mode For system evaluation purposes the UJA1069 offers the Forced normal mode. This mode is strictly for evaluation purposes only. In this mode the characteristics as defined in Section 9 In Forced normal mode the SBC behaves as follows: • SPI access (writing and reading) is blocked • ...
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... Rev. 03 — 10 September 2007 LIN fail-safe system basis chip Min 0.3 500 0.3 500 ms - 0.3 1.5 0.3 0.3 1.5 60 0.3 0.3 150 [ [2] 40 [3] [4] 8.0 2.0 [5] 200 = amb d UJA1069 Max Unit +60 V +60 V +33 V + 0.3 V BAT42 V + 0.3 V BAT42 V + 1.2 V BAT42 + +15 V +100 V ...
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... K/W 23 K/W 6 K/W T (heat sink) case R th(c-a) T amb 001aad671 V1 dissipation V3 dissipation 6 K/W 17 K/W 6 K/W T (heat sink) case R th(c-a) T amb Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip other dissipation K/W other dissipation K/W 001aae136 © NXP B.V. 2007. All rights reserved ...
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... V BAT14 INH/LIMP enabled; ILEN = INH/LIMP for normal output current capability at V1 for high output current capability at V1 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip unless otherwise specified. All BAT14 [1] Min Typ Max - 50 70 ...
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... V1RTHC[1: BAT14 V1RTHC[1: BAT14 V1RTHC[1: BAT14 V1RTHC[1: VFIE = 1 BAT14 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip unless otherwise specified. All BAT42 BAT14 [1] Min Typ Max 1 2 ...
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... BAT42 BAT14 [1] Min Typ 200 135 200 110 - - - - - 165 - - 0.7 - 1.2 0 2 130 50 130 UJA1069 Max Unit 120 150 1 5 400 k 400 k © NXP B.V. 2007. All rights reserved ...
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... LIN fail-safe system basis chip unless otherwise specified. All BAT42 BAT14 [1] Min Typ 1 1000 - 1.6 - 0 1.6 - UJA1069 Max Unit + © ...
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... V BAT42 0. BAT42 0.475 0.500 V V BAT42 BAT42 [ BAT42 BAT42 1.0 0 BAT42 BAT42 1.2 1.0 - 0.65 UJA1069 Max Unit 0. BAT42 2.1 V + BAT42 - V 0.175 V V BAT42 0.525 V V BAT42 + BAT42 0.2 - ...
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... Software development mode for entering Forced normal mode between pin TEST and GND Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip unless otherwise specified. All BAT42 BAT14 [1] Min Typ Max 150 ...
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... 100 120 mA 250 150 C. j Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip 001aaf215 type 5V0 type 3V3 type 3V0 (V) BAT14 001aaf244 type 5V0 type 3V3 type 3V0 (V) BAT14 © ...
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... C, +25 C and +150 ( BAT14 2 (2) 5 100 = +150 C. j Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip 001aaf246 T = +150 +25 C +150 C + 150 200 250 I (mA) V1 001aaf247 150 200 ...
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... 150 150 C (1) 5.5 V 150 120 mA. V1 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip 001aaf245 80 120 I (mA) V1 001aaf248 (Hz) © NXP B.V. 2007. All rights reserved. 160 ...
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... ESR = 0. 100 200 ESR = 0. BAT14 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip 300 400 300 400 © NXP B.V. 2007. All rights reserved. 001aaf250 200 V ...
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... Fig 22. V1 output stability related to ESR value of output capacitor UJA1069_3 Product data sheet stable operation area 2 10 unstable operation area Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip 001aaf249 80 120 I (mA) V1 © NXP B.V. 2007. All rights reserved ...
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... BAT 5.5 V BAT BAT 0 0 0.4 0 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip load SBC 100 load nF 0.1 GND 001aaf572 001aaf573 type 5V0 type 3V3 type 3V0 1.2 1 001aaf574 type 5V0 ...
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... RXDL rising edge with respect to falling edge RXDL Off-line mode Active mode LIN Active mode Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip unless otherwise specified. All BAT14 Min Typ Max [2] 24) 960 - - 240 ...
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... RSTN pin remains LOW INTN = LOW after internal or external reset has been released; RLC = 0 after internal or external reset has been released; RLC =1 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip unless otherwise specified. All BAT42 BAT14 [1] ...
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... Figure 25 and Figure t T lead cyc t t SCKH SCKL MSB X floating X MSB Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip unless otherwise specified. All BAT42 BAT14 [1] Min Typ Max 460.8 512 563.2 26. t lag LSB t ...
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... Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip 001aad179 V th(reces)(max) thresholds of receiving node 1 V th(dom)(max) V th(reces)(min) thresholds of receiving node 2 V th(dom)(min) ...
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... Rev. 03 — 10 September 2007 LIN fail-safe system basis chip detail 8.3 0.75 0.65 1 0.2 0.1 7.9 0.50 EUROPEAN PROJECTION UJA1069 SOT549 0.78 8 0.1 o 0.48 0 ISSUE DATE 03-04-07 05-11-02 © NXP B.V. 2007. All rights reserved ...
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... JEITA MO-153 Rev. 03 — 10 September 2007 LIN fail-safe system basis chip detail 6.6 0.75 0.5 1 0.2 0.13 0.1 6.2 0.50 0.2 EUROPEAN PROJECTION UJA1069 SOT864 ISSUE DATE 04-09-23 05-12-06 © NXP B.V. 2007. All rights reserved ...
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... Solder bath specifications, including temperature and impurities UJA1069_3 Product data sheet Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 29. Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip Figure 29) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... MSL: Moisture Sensitivity Level Data sheet status Product data sheet Preliminary data sheet Objective data sheet Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip peak temperature Change notice Supersedes - UJA1069_2 Table 20 and Table 21 Table 5, Table 11 and Table 22. - UJA1069_1 - - © ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UJA1069 All rights reserved. Date of release: 10 September 2007 Document identifier: UJA1069_3 ...