uja1069 NXP Semiconductors, uja1069 Datasheet - Page 24

• Manufacturer Part Number: uja1069
• Description: Lin Fail-safe System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1069_3
Product data sheet
Fig 14. SPI timing protocol
SDO
SCS
SCK
SDI
6.12 SPI interface
floating
X
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave and multi-master operation. The SPI is configured
for full duplex data transfer, so status information is returned when new control data is
shifted in. The interface also offers a read-only access option, allowing registers to be
read back by the application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge; see
To protect against wrong or illegal SPI instructions, the SBC detects the following SPI
failures:
X
•
•
•
•
•
•
•
sampled
SCS - SPI chip select; active LOW
SCK - SPI clock; default level is LOW due to low-power concept
SDI - SPI data input
SDO - SPI data output; floating when pin SCS is HIGH
SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock
cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.
In Start-up and Restart mode a reset is forced instead of an interrupt
Forbidden mode changes according to
Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see
01
MSB
MSB
Figure
02
14.
14
14
Rev. 03 — 10 September 2007
03
13
13
04
12
12
Figure 4
Section 6.12.3
15
01
01
result in an immediate system reset
LIN fail-safe system basis chip
16
LSB
LSB
UJA1069
© NXP B.V. 2007. All rights reserved.
floating
mce634
X
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