uja1069 NXP Semiconductors, uja1069 Datasheet - Page 31

• Manufacturer Part Number: uja1069
• Description: Lin Fail-safe System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 8.
[1]
[2]
UJA1069_3
Product data sheet
Bit
7
6
5
4
3
2
1
0
This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required
(fail-safe behavior).
WEN (in the System Configuration register) has to be set to activate the WAKE port function globally.
Interrupt Enable and Interrupt Enable Feedback register bit description
Symbol
BATFIE
VFIE
-
LINFIE
WIE
WDRIE
-
LINIE
6.12.7 Interrupt register
The Interrupt register allows the cause of an interrupt event to be read. The register is
cleared upon a read access and upon any reset event. Hardware ensures that no interrupt
event is lost in case there is a new interrupt forced while reading the register. After reading
the Interrupt register pin INTN is released for t
INTN.
The interrupts can be classified into two groups:
•
•
Description
BAT Failure Interrupt
Enable
Voltage Failure Interrupt
Enable
reserved
LIN Failure Interrupt
Enable
WAKE Interrupt
Enable
Watchdog Restart
Interrupt Enable
reserved
LIN Interrupt Enable
Timing critical interrupts which require immediate reaction (SPI clock count failure
which needs a new SPI command to be resent immediately, and a BAT failure which
needs critical data to be saved immediately into the nonvolatile memory)
Interrupts which do not require an immediate reaction (overtemperature and LIN
failures, V1 and V3 failures and the wake-ups via LIN and WAKE. These interrupts will
be signalled in Normal mode to the microcontroller once per watchdog period
(maximum); this prevents overloading the microcontroller with unexpected interrupt
events (e.g. a chattering LIN failure). However, these interrupts are reflected in the
interrupt register
[2]
Rev. 03 — 10 September 2007
Value
1
0
1
0
0
1
0
1
0
1
0
0
1
0
Function
falling edge at SENSE forces an interrupt
no interrupt forced
clearing of V1D or V3D forces an interrupt
no interrupt forced
reserved for SBCs with CAN transceiver
any change of the LIN Failure status bits forces an interrupt
no interrupt forced
a negative edge at pin WAKE generates an interrupt in
Normal mode, Flash mode or Standby mode
a negative edge at pin WAKE generates a reset in Standby
mode; no interrupt in any other mode
a watchdog restart during watchdog OFF generates an
interrupt
no interrupt forced
reserved for SBCs with CAN transceiver
LIN-bus event results in a wake-up interrupt in Standby
mode and in Normal or Flash mode (unless LIN is in Active
mode already)
LIN-bus event results in a reset in Standby mode; no
interrupt in any other mode
INTN
to guarantee an edge event at pin
LIN fail-safe system basis chip
…continued
UJA1069
© NXP B.V. 2007. All rights reserved.
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