SST25VF080-33-4C-QA Silicon Storage Technology, Inc., SST25VF080-33-4C-QA Datasheet
SST25VF080-33-4C-QA
Related parts for SST25VF080-33-4C-QA
SST25VF080-33-4C-QA Summary of contents
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... The SST25VF080 devices operate with a single 2.7-3.6V power supply. The SST25VF080 devices are offered in an 8-lead SOIC package with 200 mil body width. See Figure 1 for pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...
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... Advance Information UNCTIONAL LOCK IAGRAM Address Buffers and Latches CE# ©2003 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF080 SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1250 B1.0 S71250-00-000 10/03 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF080 DD V Ground SS ©2003 Silicon Storage Technology, Inc. CE# ...
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... BFH Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). 80H The SST25VF080 supports both Mode 0 (0,0) and Mode 3 T2.0 1250 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... W OLD ONDITION Write Protection SST25VF080 provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 5 for Block-Protection description ...
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... Silicon Storage Technology, Inc. 8 Mbit SPI Serial Flash Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Default at Power- SST25VF080 Read/Write R R R/W R/W N/A R R/W T4.0 1250 S71250-00-000 10/03 ...
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... Mbit SPI Serial Flash SST25VF080 Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table software pro- tected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0 ...
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... Advance Information Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25VF080. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
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... Mbit SPI Serial Flash SST25VF080 Read The Read instruction supports MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until ter- minated by a low to high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached ...
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... Byte-Program operation. See Figure 5 for the Byte-Program sequence ADD. ADD. MSB MSB HIGH IMPEDANCE 10 8 Mbit SPI Serial Flash SST25VF080 -A ]. Following the 23 0 for the completion of the internal ADD MSB LSB 1250 F05 ...
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... Mbit SPI Serial Flash SST25VF080 Auto Address Increment (AAI) Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total program- ming time when the entire memory array pro- grammed ...
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... Erase cycle. See Figure 8 for the Block-Erase sequence ADD. ADD. MSB MSB HIGH IMPEDANCE 12 8 Mbit SPI Serial Flash SST25VF080 ), remaining address bits can for the completion of the internal self ADD. 1250 F07.0 ]. Address bits [ Most ...
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... Mbit SPI Serial Flash SST25VF080 Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence ...
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... SCK MODE MSB HIGH IMPEDANCE SO 1250 F12.0 EQUENCE Status-Register (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed Mbit SPI Serial Flash SST25VF080 S71250-00-000 10/03 ...
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... Mbit SPI Serial Flash SST25VF080 Write-Status-Register (WRSR) The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register (EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-Status-Register instruction must be executed immediately after the execution of the Enable- Write-Status-Register instruction (very next instruction bus cycle) ...
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... Advance Information Read-ID The Read-ID instruction identifies the devices as SST25VF080 and manufacturer as SST. The device infor- mation can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Read-ID instruction, the manufacturer’ located in CE# MODE ...
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... Mbit SPI Serial Flash SST25VF080 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
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... T Chip-Erase SCE T Byte-Program BP 1. Relative to SCK. ©2003 Silicon Storage Technology, Inc. Minimum Specification 10,000 100 100 + I DD Parameter 18 8 Mbit SPI Serial Flash SST25VF080 Test Condition Maximum OUT T9.0 1250 Units Test Method Cycles JEDEC Standard A117 Years ...
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... Mbit SPI Serial Flash SST25VF080 CE# T CHH T CES SCK MSB SI SO HIGH-Z FIGURE 15 ERIAL NPUT IMING CE# T SCKH SCK T CLZ SO SI FIGURE 16 ERIAL UTPUT IMING ©2003 Silicon Storage Technology, Inc. T SCKF T SCKR D IAGRAM T SCKL T OH ...
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... All commands are rejected by the device. V Min DD FIGURE 18 OWER UP IMING ©2003 Silicon Storage Technology, Inc HHH HLS T HLH PU-READ T PU-WRITE D IAGRAM 20 8 Mbit SPI Serial Flash SST25VF080 T HHS T LZ Device fully accessible Time 1250 F18.0 S71250-00-000 1250 F17.0 10/03 ...
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... Mbit SPI Serial Flash SST25VF080 V IHT INPUT V ILT AC test inputs are driven at V (0.9V IHT for inputs and outputs are V (0.7V HT FIGURE 19 NPUT UTPUT FIGURE 20 EST OAD XAMPLE ©2003 Silicon Storage Technology, Inc REFERENCE POINTS for a logic “1” and V (0 ...
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... LF 080 - XX XX XXXX X - XXX Valid combinations for SST25VF080 SST25VF080-20-4C-S2A SST25VF080-20-4C-S2AE SST25VF080-20-4I-S2A SST25VF080-20-4I-S2AE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ...
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... Mbit SPI Serial Flash SST25VF080 PACKAGING DIAGRAMS Pin #1 TOP VIEW Identifier 5.40 5.15 5.40 5.15 8.10 7.70 Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads LEAD MALL UTLINE NTEGRATED SST S2A ACKAGE ...