SST25VF080-33-4C-QA Silicon Storage Technology, Inc., SST25VF080-33-4C-QA Datasheet - Page 7

• Manufacturer Part Number: SST25VF080-33-4C-QA
• Description: Voltage = 2.7 to 3.6 ;; Density = 8Mb ;; Organization = 1Mb X 8 ;; Speed = 0 - 20 MHZ ;; Temp. = Commercial ;; Package = Qfn/wson
• Manufacturer: Silicon Storage Technology, Inc.

8 Mbit SPI Serial Flash
SST25VF080
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table 5, to be software pro-
tected against any memory Write (Program or Erase)
operations. The Write-Status-Register (WRSR) instruction
is used to program the BP1 and BP0 bits as long as WP#
is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase
can only be executed if Block-Protection bits are both 0.
After power-up, BP1 and BP0 are set to 1.
TABLE 5: S
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit pro-
vides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
©2003 Silicon Storage Technology, Inc.
1. Default at power-up for BP1 and BP0 is ‘11’.
3 (Full Memory Array)
1 (1/4 Memory Array)
2 (1/2 Memory Array)
Protection Level
OFTWARE
0
S
TATUS
R
EGISTER
BP1
0
0
1
1
Register
Status
Bit
B
LOCK
BP0
0
1
0
1
P
ROTECTION
Protected Memory Area
7
0C0000H-0FFFFFH
080000H-0FFFFFH
000000H-0FFFFFH
Block Protection Lock-Down (BPL)
WP# pin driven low (V
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the
WP# pin is driven high (V
its value is “Don’t Care”. After power-up, the BPL bit is
reset to 0.
1
8 Mbit
None
T5.0 1250
IL
), enables the Block-Protection-
IH
), the BPL bit has no effect and
Advance Information
S71250-00-000
10/03