SST25VF080-33-4C-QA Silicon Storage Technology, Inc., SST25VF080-33-4C-QA Datasheet - Page 8

• Manufacturer Part Number: SST25VF080-33-4C-QA
• Description: Voltage = 2.7 to 3.6 ;; Density = 8Mb ;; Organization = 1Mb X 8 ;; Speed = 0 - 20 MHZ ;; Temp. = Commercial ;; Package = Qfn/wson
• Manufacturer: Silicon Storage Technology, Inc.

Advance Information
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VF080. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
TABLE 6: D
©2003 Silicon Storage Technology, Inc.
Cycle Type/
Operation
Read
Sector-Erase
Block-Erase
Chip-Erase
Byte-Program
Auto Address Increment
(AAI) Single-Byte Program
Read-Status-Register
(RDSR)
Enable-Write-Status-Register
(EWSR)
Write-Status-Register
(WRSR)
Write-Enable (WREN)
Write-Disable (WRDI)
Read-ID
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of
11. Manufacturer’s ID is read with A
12. Device ID = 80H for SST25VF080
1. A
2. Operation: S
3. X = Dummy Input Cycles (V
4. One bus cycle is eight clock periods.
5. Sector addresses: use A
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction
7. Block addresses for: use A
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
A
Address bits above the most significant bit of each density can be V
- = Non-Applicable Cycles (Cycles are not necessary)
must be executed.
followed by the data to be programmed.
each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
ID output stream is continuous until terminated by a low to high transition on CE#
MS
MS
10
10
= A
= Most Significant Address
2,3
6
5,7
19
5,6
6
for SST25VF080
EVICE
IN
= Serial In, S
O
PERATION
6,8
MS
MS
-A
IL
OUT
90H or
12
-A
or V
ABH
AFH
03H
20H
52H
60H
02H
05H
50H
01H
06H
04H
S
, remaining addresses can be V
15
0
= Serial Out
=0, and Device ID is read with A
IN
, remaining addresses can be V
I
IH
NSTRUCTIONS
);
1
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
A
A
A
A
A
23
23
23
23
23
Data
00H
S
1
X
-A
-A
-A
-
-A
-A
-
-
-
IN
16
16
16
16
16
2
S
D
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
OUT
-
-
-
-
IL
8
0
or V
IL
=1. All other address bits are 00H. The Manufacturer and Device
A
A
A
A
A
or V
IL
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
00H
15
15
15
15
15
S
IH
or V
-
-
-
-
-
-
IN
-A
-A
-A
-A
-A
IH
8
8
8
8
8
IH
3
Bus Cycle
Note
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
-
-
-
-
-
9
Addr
A
A
A
A
A
4
S
7
7
7
7
7
ID
-.
-A
-A
-A
-
-A
-A
-
-
-
-
IN
11
0
0
0
0
0
4
8 Mbit SPI Serial Flash
Note
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
-
-
-
-
-
9
D
D
S
X
X
-
-
-
-
-
-
-
-
IN
IN
IN
D
5
Note
S
D
Hi-Z
Hi-Z
SST25VF080
OUT
S71250-00-000
OUT
OUT
-
-
-
-
-
-
-
12
9
S
IN
T6.0 1250
6
S
OUT
10/03