LTC1417 LINER [Linear Technology], LTC1417 Datasheet

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... The low 20mW power dissipation is made even more attractive with two user- selectable power shutdown modes. The LTC1417 converts 0V to 4.096V unipolar inputs when using a 5V supply and 2.048V bipolar inputs when using 5V supplies. DC specs include 1.25LSB INL, 1LSB DNL and no missing codes over temperature ...

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... Bipolar Operation.........................(V Digital Output Voltage Unipolar Operation ................... – 0 Bipolar Operation........... (V – 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range LTC1417C .............................................. LTC1417I ............................................ – Storage Temperature Range ................ – 150 C Lead Temperature (Soldering, 10 sec)................. 300 VERTER C HARA TERISTICS C temperature range, otherwise specifications are at T otherwise noted ...

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... V = 4.75V 160 4.75V – 1.6mA High OUT DD RD High (Note OUT OUT DD LTC1417 MIN TYP MAX 14 3 150 500 –1 MIN TYP MAX 79 81 – 85 – 95 – 98 – 0.8 indicates specifications which apply over the full ...

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... LTC1417 W U POWER REQUIRE E TS otherwise specifications are (Note 5) A SYMBOL PARAMETER V Positive Supply Voltage (Notes 10, 11 Negative Supply Voltage (Note 10 Positive Supply Current DD Nap Mode Sleep Mode I Negative Supply Current SS Nap Mode Sleep Mode P Power Dissipation ...

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... Differential Nonlinearity vs Output Code 1.0 0.5 0 – 0.5 –1.0 0 4096 8192 12288 OUTPUT CODE LTC1417 MIN TYP MAX 10 10 0. 10MHz for rising SCLK up to 20MHz for falling capture with SCLK ( ...

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... LTC1417 W U TYPICAL PERFOR A CE CHARACTERISTICS Signal-to-Noise Ratio vs Input Frequency 10k 100k 1M INPUT FREQUENCY (Hz) 1417 G04 Nonaveraged, 4096 Point FFT, Input Frequency = 10kHz 400kHz SAMPLE f = 10.05859375kHz IN –20 SFDR = –97.44dB SINAD = 81.71dB –40 –60 – ...

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... Nap mode and for Sleep mode. RD (Pin 12): Read Input. This enables the output drivers. RD also sets the shutdown mode when SHDN goes low. RD and SHDN low selects the quick wake-up Nap mode, RD high and SHDN low selects Sleep mode. LTC1417 V Supply Current vs SS Temperature (Bipolar Mode) 3 ...

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... LTC1417 PIN FUNCTIONS CONVST (Pin 13): Conversion Start Signal. This active low signal starts a conversion on its falling edge. BUSY (Pin 14): The BUSY output shows the converter status low when a conversion is in progress. TEST CIRCUITS Load Circuits for Access Timing D D OUT ...

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... SHIFT a low distortion sine wave and analyzing the digital output D OUT REGISTER using an FFT algorithm, the ADC’s spectral content can be 1417 F01 examined for frequencies beyond the fundamental. Figure 3 shows a typical LTC1417 FFT plot. LTC1417 + and – and ...

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... DC and half the sampling frequency. THD is expressed as: THD where V1 is the RMS amplitude of the fundamental fre- quency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure 5. The LTC1417 has good distortion performance up to the Nyquist frequency and beyond ...

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... During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1417 inputs can be driven directly. As source impedance increases, so will acquisition time (see Figure 7). For minimum acquisition time, with high source impedance, a buffer amplifier must be used ...

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... If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1417 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifica- tions are most critical and time domain applications where DC accuracy and settling time are most critical ...

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... Input Range The 2.048V and 0V to 4.096V input ranges of the LTC1417 are optimized for low noise and low distortion. Most op amps also perform well over these ranges, allowing direct coupling to the analog inputs and eliminat- ing the need for special translation circuitry. ...

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... For full-scale adjustment, an input voltage of 2.047625V (FS – 1.5LSBs) is applied to A the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. BOARD LAYOUT AND GROUNDING To obtain the best performance from the LTC1417, a printed circuit board with ground plane is required. The R7 48k 5V ...

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... A leads IN IN – POWER SHUTDOWN input can be IN The LTC1417 provides two power shutdown modes, Nap + and IN and Sleep, to save power during inactive periods. The – (Pin 2) should be IN Nap mode reduces ADC power dissipation by 80% and leaves only the digital logic and reference powered up. ...

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... LT1363CN8 LT1363CS8 – – OPTIONAL 0 16V –5A U1 LTC1417CGN – BUSY REF 4 13 REFCOMP CONVST 5 12 AGND EXTCLKIN SHDN JP4 7 10 ...

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... To enable the serial data output buffer and shift clock, RD must be low. Figure 15 shows a function block diagram of the LTC1417. There are two pieces to this circuitry: the conversion clock selection circuit (EXTCLKIN and CLKOUT) and the serial ...

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... The largest hold time margin is achieved if data is captured on the rising edge of SCLK. BUSY gives the end-of-conversion indication. When the LTC1417 is configured as a serial bus master, BUSY can be used as a framing pulse. To three-state the serial port after transferring the serial output data, BUSY and RD should be connected together at the ADC (see Figure 17) ...

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... Using Internal Clock for Conversion and Data Transfer. Figure 17 shows data from the previous conversion being clocked out during the conversion with the LTC1417 internal clock providing both the conversion clock and the SCLK. The internal clock has been optimized for the fastest ...

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... Using an external clock to transfer data while an internal clock controls the conversion process is not recom- mended. As both signals are asynchronous, clock noise can corrupt the conversion result. BUSY (= RD CONVST BUSY 12 RD LTC1417 EXTCLKIN ( = SCLK) 6 EXTCLKIN 7 SCLK D OUT 9 D OUT t ...

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... CONVST BUSY 12 RD LTC1417 7 SCLK 9 D OUT D13 LTC1417 TM compatible. It also allows operation when after data transfer. If OUT INT DSP SCK MISO t 5 SAMPLE FILL ...

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... EXTCLKIN. The external SCLK is applied to SCLK. RD can be used to gate the external SCLK such that data will be clocked out only after RD goes low CONVST EXTCLKIN 14 BUSY LTC1417 SCLK 9 D OUT ...

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... DGND Figure 21 4.096V, 8-Channel Data Acquisition System Configured for Control and Data Retrieval by a 68HC11 C. Code is Shown in Listing A the LTC1417. The end of conversion is signaled by a logic high on the BUSY output. When this occurs, data is exchanged between the LTC1417/LTC1391 and the controller ...

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... RAM variables to hold the LTC1417’s 14 conversion result * DIN1 EQU $00 This memory location holds the LTC1417’s bits DIN2 EQU $01 This memory location holds the LTC1417’s bits MUX EQU $02 This memory location holds the MUX address data * ******************************************* * Start GETDATA Routine ******************************************* ...

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... Branch to the loop’s beginning while Bit7 remains * low * ************************************************************************* * This routine sends data to the LTC1417 and sets its MUX channel. The * very first time this routine is entered produces invalid data. Each * time thereafter, the data will correspond to the previous active * CONVST signal sent to the LTC1417. ************************************************************************* ...

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... Figure 22. This Diagram Shows the Relationship Between the Selected LTC1391 MUX Channel and the Conversion Data Retrieved from the LTC1417 When Using the Sample Program in Listing A. At Any Point in Time, a Two Conversion Delay Exists Between the Selected MUX Channel and When Its Data Is Retrieved ...

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... U TYPICAL APPLICATIONS Figure 23 uses the DG408 to select one of eight 2.048V bipolar signals and apply it to the LTC1417’s analog input. The circuit is designed to connect to a 68HC11 C. The MUX’s parallel input is connected to the controller’s port C and the LTC1417’s serial interface is accessed through the controller’ ...

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... LTC1417 U TYPICAL APPLICATIONS Listing B ************************************************************************* * * This example program selects a DG408 MUX channel using parallel * port C, initiates a conversion, and retrieves data from the LTC1417 stores the 14-bit, right justified data in two consecutive memory * locations. * ************************************************************************* * ***************************************** * 68HC11 register definitions ***************************************** * PIOC EQU $1002 Parallel I/O control register * “ ...

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... Branch to the loop’s beginning while Bit7 * remains high * ************************************************************************* * This routine sends data to the LTC1417 and sets its MUX channel. The * very first time this routine is entered produces invalid data. Each * time thereafter, the data will correspond to the previous active * CONVST signal sent to the LTC1417. ************************************************************************* ...

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... OUT MUX CH0 DATA Figure 24. Using the Sample Program In Listing 2, the LTC1417, Combined with the DG408 8-Channel MUX, Has No Latency Between the Selected Input Voltage and Its Conversion Data as Shown In the Timing Relationship Above 30 This sets the SS* output bit to a logic ...

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... TYP 0.008 – 0.012 (0.203 – 0.305) LTC1417 0.189 – 0.196* (4.801 – 4.978) 0.009 (0.229 REF 0.150 – 0.157** (3.810 – 3.988) ...

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... LTC1417 RELATED PARTS PART NUMBER DESCRIPTION ADCs LTC1274/LTC1277 Low Power, 12-Bit, 100ksps ADCs with Parallel Output LTC1401 Serial 3V, 12-Bit, 200ksps ADC in SO-8 LTC1404 Serial 12-Bit, 600ksps ADC is SO-8 LTC1412 12-Bit, 3Msps Sampling ADC with Parallel Output LTC1415 Single 5V, 12-Bit, 1.25Msps ADC with Parallel Output ...