LTC1417 LINER [Linear Technology], LTC1417 Datasheet - Page 28

• Manufacturer Part Number: LTC1417
• Description: Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O
• Manufacturer: LINER [Linear Technology]

LTC1417
TYPICAL APPLICATIONS
Listing B
*************************************************************************
*
* This example program selects a DG408 MUX channel using parallel
* port C, initiates a conversion, and retrieves data from the LTC1417.
* It stores the 14-bit, right justified data in two consecutive memory
* locations.
*
*************************************************************************
*
*****************************************
* 68HC11 register definitions
*****************************************
*
PIOC
*
PORTC
*
DDRC
*
*
PORTD
*
DDRD
SPCR
*
SPSR
*
SPDR
*
* RAM variables to hold the LTC1417’s 14 conversion result
*
DIN1
DIN2
MUX
*
*****************************************
* Start GETDATA Routine
*****************************************
*
INIT1
*
*
*
*
*
*
*
*
*
* DDRD’s Bit5 is a 1 so that port D’s SS* pin is a general output
*
*
28
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
ORG
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
$1002
$1003
$1007
$1008
$1009
$1028
$1029
$102A
$00
$01
$02
$C000
#$03
PIOC
#$47
DDRC
#$2F
PORTD
#$38
DDRD
#$50
SPCR
Parallel I/O control register
“STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB”
Port C data register
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
Port D data direction register
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
1 = output, 0 = input
Port D data register
“ -
Port D data direction register
SPI control register
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPI status register
“SPIF,WCOL, -
SPI data register; Read-Buffer; Write-Shifter
This memory location holds the LTC1417’s bits 13 - 08
This memory location holds the LTC1417’s bits 07 - 00
This memory location holds the MUX address data
Program start location
0,0,0,0,0,0,1,1
“STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1”
Ensures that the PIOC register’s status is the same
as after a reset, necessary of simple Port D manipulation
0,1,0,0,0,1,1,1
“Bit7=input,Bit6=output,- ,- ,- ,Bit2=output,Bit1=output,
Bit0=output”
Bit7 used for BUSY input
Bit6 used for CONVST signal output
Bits 2 - 0 are used for the MUX address
Direction of PortD’s bit are now set
-,-,1,0;1,1,1,1
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
Keeps SS* a logic high when DDRD, Bit5 is set
-,-,1,1;1,0,0,0
SS* , SCK, MOSI are configured as Outputs
MISO, TxD, RxD
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
(This assumes an E-Clock frequency of 4MHz. For higher
, -
U
, SS* ,CSK ;MOSI,MISO,TxD ,RxD “
,MODF; -
are configured as Inputs
*
*
, -
, -
, -
“
*
*
*
*
*
*