LTC1417 LINER [Linear Technology], LTC1417 Datasheet - Page 24

• Manufacturer Part Number: LTC1417
• Description: Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O
• Manufacturer: LINER [Linear Technology]

LTC1417
Listing A
***********************************************************************
*
* This example program retrieves data from a previous LTC1417
* conversion and loads the next LTC1391 MUX channel. It stores the
* 14-bit, right justified data in two consecutive memory locations.
* It finishes by initiating the next conversion.
*
***********************************************************************
*
************************************
* 68HC11 register definitions
************************************
*
PIOC
*
PORTC
*
DDRC
*
*
PORTD
*
DDRD
SPCR
*
SPSR
*
SPDR
*
* RAM variables to hold the LTC1417’s 14 conversion result
*
DIN1
DIN2
MUX
*
*******************************************
* Start GETDATA Routine
*******************************************
*
INIT1
*
*
*
*
*
*
*
* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
*
TYPICAL APPLICATIONS
24
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
ORG
LDAA
STAA
LDAA
STAA
LDAA
ORAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
$1002
$1003
$1007
$1008
$1009
$1028
$1029
$102A
$00
$01
$02
$C000
#$03
PIOC
#$01
DDRC
PORTC
#%00000001
PORTC
#$2F
PORTD
#$38
DDRD
#$50
SPCR
Parallel I/O control register
“STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB”
Port C data register
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
Port D data direction register
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
1 = output, 0 = input
Port D data register
“ -
Port D data direction register
SPI control register
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPI status register
“SPIF,WCOL, -
SPI data register; Read-Buffer; Write-Shifter
This memory location holds the LTC1417’s bits 13 - 08
This memory location holds the LTC1417’s bits 07 - 00
This memory location holds the MUX address data
Program start location
0,0,0,0,0,0,1,1
“STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1”
Ensures that the PIOC register’s status is the same
as after a reset, necessary of simple Port D manipulation
0,0,0,0,0,0,0,1
“Bit7=input,- ,- ,- ,- ,- ,- ,Bit0=output”
Bit7 used for BUSY signal input, Bit0 used for CONVST
signal output
The direction of PortD’s bits are now set
Get contents of Port C
Initialize CONVST to a logic high
-,-,1,0;1,1,1,1
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
Keeps SS* a logic high when DDRD, bit 5 is set
-,-,1,1;1,0,0,0
SS* , SCK, MOSI are configured as Outputs
MISO, TxD, RxD
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
, -
Set Bit0 high
U
, SS* ,CSK ;MOSI,MISO,TxD ,RxD “
*
,MODF; -
are configured as Inputs
*
, -
, -
, -
“
*
*
*
*
*
*