LMK03000 National Semiconductor Corporation, LMK03000 Datasheet
LMK03000
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LMK03000 Summary of contents
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... RMS ( MHz). When configured as a jitter cleaner, the LMK03000C/LMK03001C features jitter performance of 400 fs RMS (12 kHz - 20 MHz) and the LMK03000C/LMK03001C 800 fs RMS (12 kHz - 20 MHz). The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family. © ...
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Functional Block Diagram Connection Diagram www.national.com 48-Pin LLP Package 2 20211401 20211402 ...
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Pin Descriptions Pin # 13, 16, 19, 22, 26, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, 30, 31, 33, 37, 40, 43, 46 Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14 34, ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Input Voltage Storage Temperature Range Lead Temperature (solder 4 s) Junction Temperature Recommended Operating Conditions ...
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... PLL_CP_GAIN = 1x PLL_CP_GAIN = 32x PLL_CP_GAIN = 1x PLL_CP_GAIN = 32x VCO LMK03000/LMK03000C LMK03001/LMK03001C After programming R15 for lock, no changes to output configuration are permitted to guarantee continuous lock. (Note 7) LMK03000/LMK03000C °C A LMK03001/LMK03001C °C A LMK03000/LMK03000C LMK03001/LMK03001C LMK03000/LMK03001 12 kHz to 20 MHz bandwidth LMK03000C/LMK03001C 12 kHz to 20 MHz bandwidth ...
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Symbol Parameter Clock Distribution Section (Note 9) - LVDS Clock Outputs (CLKout0 to CLKout2) Jitter Additive RMS Jitter (Note 9) ADD t CLKoutX to CLKoutY (Note 10) SKEW V Differential Output Voltage OD Change in magnitude of V ΔV OD ...
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Symbol Parameter t Data to Clock Set Up Time CS t Data to Clock Hold Time CH t Clock Pulse Width High CWH t Clock Pulse Width Low CWL t Clock to Enable Set Up Time ES t Enable to ...
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Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current Charge Pump Sink Current Charge Pump Sink Current Charge Pump Source Current Charge ...
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... Two VCO frequency plans are available for each performance grade. The LMK03000 and LMK03000C include a 1.24 GHz VCO. The LMK03001 and LMK03001C include a 1.52 GHz VCO. The VCO output is optionally accessible on the Fout port ...
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GLOBAL OUTPUT ENABLE AND LOCK DETECT The GOE pin provides an internal pull-up resistor un- terminated externally, the clock output states are determined by the Clock Output Enable bits (CLKoutX_EN) and the EN_CLKout_Global bit. www.national.com By ...
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... General Programming Information The LMK03000/LMK03000C/LMK03001/LMK03001C devices are programmed using several 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0]. ...
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CLKout0_EN CLKout1_EN CLKout2_EN CLKout3_EN CLKout4_EN CLKout5_EN CLKout6_EN CLKout7_EN RESET Register www.national.com 12 ...
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DIV4 POWERDOWN EN_CLKout_Global EN_Fout Register 13 www.national.com ...
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REGISTER Registers R0 through R7 control the eight clock output pins. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the ...
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CLKoutX_DLY[3:0] -- Clock Output Delays These bits control the delay stages for each clock output pin. In order for these delays to be active, the respective CLKoutX_MUX (See 2.2.2) bit must be set to either "Delayed" or "Divided and ...
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REGISTER R13 2.4.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter Capacitors C3 and C4 These bits control the capacitor values for C3 and C4 in the internal loop filter. VCO_C3_C4_LF[3:0] 2.4.2 VCO_R3_LF[2:0] -- Value for Internal Loop Filter Resistor ...
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OSCin_FREQ[7:0] -- Oscillator Input Calibration Adjustment These bits are to be programmed to the OSCin frequency. If the OSCin frequency is not an integral multiple of 1 MHz, then round to the closest value. OSCin_FREQ[7:0] 200 201 to 255 ...
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EN_CLKout_Global bit -- Global Clock Output Enable This bit overrides the individual CLKoutX_EN bits (See 2.2.5). When this bit is set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or ...
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PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain These bits set the charge pump gain of the PLL. PLL_CP_GAIN[1: Charge Pump Gain 1x 4x 16x 32x 19 www.national.com ...
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Application Information 3.1 SYSTEM LEVEL DIAGRAM The following shows the LMK300xx in a typical application. In this setup the clock may be multiplied, reconditioned, and redis- tributed. The first and second pole of the loop filter are external. The ...
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LOOP FILTER The internal charge pump is directly connected to the integrated loop filter components. The first and second pole of the loop filter are externally attached as shown in Figure 2. When the loop filter is designed, it ...
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CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the follow table serves to provide enough information to allow the user to calculate estimated current consumption of the device. Unless otherwise noted Vcc = 3.3 ...
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FIGURE 3. Recommended Land and Via Pattern To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area ...
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... Package Marking LMK03000ISQ K03000 I LMK03000ISQX K03000 I LMK03001ISQ K03001 I LMK03001ISQX K03001 I LMK03000CISQ K03000CI LMK03000CISQX K03000CI LMK03001CISQ K03001CI LMK03001CISQX K03001CI www.national.com inches (millimeters) unless otherwise noted Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package Packing VCO Version 250 Unit Tape and Reel 1 ...
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Notes 25 www.national.com ...
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