LMK03000 National Semiconductor Corporation, LMK03000 Datasheet - Page 18

• Manufacturer Part Number: LMK03000
• Manufacturer: National Semiconductor Corporation

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2.5.4 EN_CLKout_Global bit -- Global Clock Output Enable
This bit overrides the individual CLKoutX_EN bits (See 2.2.5). When this bit is set to 0, all clock outputs are disabled, regardless
of the state of any of the other bits or pins. See 1.8 for more information on CLKout states.
2.5.5 EN_Fout bit -- Fout port enable
This bit enables the Fout pin.
2.6 Register R15
Programming R15 also activates the frequency calibration routine.
2.6.1 PLL_N[17:0] -- PLL N Divider
These bits program the divide value for the PLL N Divider. The PLL N Divider follows the Input Divider and precedes the PLL phase
detector. Since the Input Divider is also in the feedback path from the VCO to the PLL Phase Detector, the total N divide value,
N
f
for PLL_N[17:0].
2.6.2 INPUT_DIV[3:0] -- Input Divider
These bits program the divide value for the Input Divider. The Input Divider follows the VCO output and precedes the clock distri-
bution blocks. Since the Input Divider is in the feedback path from the VCO to the PLL phase detector the Input Divider contributes
to the total N divide value, N
Divider) for more information on setting the VCO frequency.
VCO
Total
0
0
1
.
= f
, is also influenced by the Input Divider value. N
OSCin
0
0
1
.
0
0
0
0
0
0
0
0
1
1
1
.
* PLL N Divider * Input Divider / R. Since the PLL N divider is a pure binary counter, there are no illegal divide values
0
0
1
.
0
0
1
.
0
0
1
.
Total
EN_CLKout_Global bit
0
0
1
.
0
0
0
0
1
1
1
1
0
0
1
.
. N
EN_Fout bit
INPUT_DIV[3:0]
Total
0
0
1
.
= PLL N Divider * Input Divider. The Input Divider can not be bypassed. See 2.5.1 (PLL N
0
1
0
1
0
0
1
.
PLL_N[17:0]
0
0
1
.
0
0
1
.
0
0
1
1
0
0
1
1
0
0
1
.
Total
0
0
1
= PLL N Divider * Input Divider. The VCO frequency is calculated as,
.
18
0
0
1
.
0
0
1
.
Normal Operation
Fout Pin Status
Clock Outputs
0
1
0
1
0
1
0
1
0
1
1
.
0
0
1
.
Disabled
Enabled
All Off
0
0
1
.
0
0
1
.
0
0
1
.
Input Divider Value
0
1
1
.
PLL N Divider Value
Invalid
Invalid
Invalid
Invalid
...
2
3
4
5
6
7
8
262143
Invalid
...
1