LMK03000 National Semiconductor Corporation, LMK03000 Datasheet - Page 9

• Manufacturer Part Number: LMK03000
• Manufacturer: National Semiconductor Corporation

1.0 Functional Description
The LMK03000/LMK03000C/LMK03001/LMK03001C preci-
sion clock conditioners combine the functions of jitter clean-
ing/reconditioning, multiplication, and distribution of a refer-
ence clock. The devices integrate a Voltage Controlled
Oscillator (VCO), a high performance Integer-N Phase
Locked Loop (PLL), a partially integrated loop filter, three
LVDS, and five LVPECL clock output distribution blocks.
When configured as a clock generator with a wide loop band-
width, a high phase detector frequency, and a low noise clock
source the LMK03000C/LMK03001C features jitter perfor-
mance of 200 fs RMS (10 Hz - 20 MHz). When configured as
a jitter cleaner, the LMK03000C/LMK03001C features jitter
performance of 400 fs RMS (12 kHz - 20 MHz) and the
LMK03000C/LMK03001C 800 fs RMS (12 kHz - 20 MHz).
The devices include internal 3rd and 4th order poles to sim-
plify loop filter design and improve spurious performance. The
1st and 2nd order poles are off-chip to provide flexibility for
the design of various loop filter bandwidths.
Two VCO frequency plans are available for each performance
grade. The LMK03000 and LMK03000C include a 1.24 GHz
VCO. The LMK03001 and LMK03001C include a 1.52 GHz
VCO. The VCO output is optionally accessible on the Fout
port. Internally, the VCO output goes through an Input Divider
to feed the various clock distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
1.1 BIAS PIN
To properly use the device, bypass Bias (pin 36) with a low
leakage 1 µF capacitor connected to Vcc. This is important
for low noise performance.
1.2 LDO BYPASS
To properly use the device, bypass LDObyp1 (pin 9) with a
10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.
1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)
The purpose of OSCin is to provide the PLL with a reference
signal. The OSCin port must be AC coupled, refer to the Sys-
tem Level Diagram in the Application Information section. The
OSCin port may be driven single endedly by AC grounding
OSCin* with a 0.1 µF capacitor.
1.4 LOW NOISE, FULLY INTEGRATED VCO
The LMK03000/LMK03000C/LMK03001/LMK03001C de-
vices contain a fully integrated VCO. In order for proper
operation the VCO uses a frequency calibration algorithm.
The frequency calibration algorithm is activated any time that
the R15 register is programmed. Once R15 is programmed
the temperature may not drift more than the maximum allow-
able drift for continuous lock, ΔT
guaranteed to stay in lock.
For the frequency calibration algorithm to work properly OS-
Cin must be driven by a valid signal when R15 is programmed.
CL
, or else the VCO is not
9
1.5 CLKout DELAYS
Each individual clock output includes a delay adjustment.
Clock output delay registers (CLKoutX_DLY) support a 150
ps step size and range from 0 to 2250 ps of total delay.
1.6 LVDS/LVPECL OUTPUTS
Each LVDS or LVPECL output may be disabled individually
by programming the CLKoutX_EN bits. All the outputs may
be disabled simultaneously by pulling the GOE pin low or
programming EN_CLKout_Global to 0.
1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
The SYNC* synchronizes the clock outputs. When SYNC* is
held in a logic low state, the outputs are also held in a logic
low state. When SYNC* goes high, the clock outputs are ac-
tivated and will transition to a high state simultaneously.
SYNC* must be held low for greater than one clock cycle of
the Input Channel Bus. Once this low event has been regis-
tered, the outputs will not reflect the low state for four more
cycles. Similarly once SYNC* becomes high, the outputs will
not simultaneously transition high until four more Input Chan-
nel Bus clock cycles have passed. See the timing diagram
below for further detail. In the timing diagram below the chan-
nels are programmed as: CLKout0_MUX = Bypassed,
CLKout1_MUX = Divided, CLKout1_DIV = 2, CLKout2_MUX
= Divided, CLKout2_DIV = 4.
SYNC* Timing Diagram
1.8 CLKout OUTPUT STATES
Each clock output may be individually enabled with the
CLKoutX_EN bits. Each individual output enable control bit is
gated with the Global Output Enable input pin (GOE) and the
Global Output Enable bit (EN_CLKout_Global).
All clock outputs can be disabled simultaneously if the GOE
pin is pulled low by an external signal or EN_CLKout_Global
is set to 0.
When an LVDS output is in the Off state, the outputs are at a
voltage of approximately 1.5 volts. When an LVPECL output
is in the Off state, the outputs are at a voltage of approximately
1 volt.
Don't care
CLKoutX
_EN bit
1
0
1
EN_CLKout
_Global bit
Don't care
1
0
1
Don't care
Don't care
GOE pin
High
0
Output State
www.national.com
Clock X
Enabled
Low
Off
Off
20211404