LMK03000 National Semiconductor Corporation, LMK03000 Datasheet - Page 17

• Manufacturer Part Number: LMK03000
• Manufacturer: National Semiconductor Corporation

2.4.4 OSCin_FREQ[7:0] -- Oscillator Input Calibration Adjustment
These bits are to be programmed to the OSCin frequency. If the OSCin frequency is not an integral multiple of 1 MHz, then round
to the closest value.
2.5 REGISTER R14
2.5.1 PLL_R[11:0] -- R Divider Value
These bits program the PLL R Divider and are programmed in binary fashion. Any changes to PLL_R require R15 to be programmed
again to active the frequency calibration routine.
2.5.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin
These bits set the output mode of the LD pin. The table below lists several different modes.
2.5.3 POWERDOWN bit -- Device Power Down
This bit can power down the device. Enabling this bit powers down the entire chip and all blocks, regardless of the state of any of
the other bits or pins.
0
0
0
1
.
0
0
0
1
.
PLL_MUX[3:0]
12 to 15
0
0
0
1
.
10
11
0
1
2
3
4
5
6
7
8
9
0
0
0
1
.
OSCin_FREQ[7:0]
POWERDOWN bit
201 to 255
0
0
0
1
.
200
...
1
2
0
1
PLL_R[11:0]
0
0
0
1
.
0
0
0
1
.
Open Drain NMOS
Open Drain PMOS
Output Type
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
0
0
0
1
.
Hi-Z
17
0
0
0
1
.
Entire Chip Powered Down
OSCin Frequency
Normal Operation
0
0
0
1
.
200 MHz
1 MHz
2 MHz
Invalid
Mode
...
Invalid
0
0
1
1
.
N Divider Output (Very Low Duty Cycle)
R Divider Output (Very Low Duty Cycle)
N Divider Output/2 (50% Duty Cycle)
R Divider Output/2 (50% Duty Cycle)
Digital Lock Detect (Active High)
Digital Lock Detect (Active Low)
0
1
0
1
.
Analog Lock Detect
Analog Lock Detect
Analog Lock Detect
LD Pin Function
Logic High
Logic Low
PLL R Divide Value
Disabled
Invalid
4095
...
1
2
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