IDT72V36104 IDT [Integrated Device Technology], IDT72V36104 Datasheet
IDT72V36104
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IDT72V36104 Summary of contents
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... Memory storage capacity: IDT72V3684 – 16,384 IDT72V3694 – 32,768 IDT72V36104 – 65,536 • • • • • Clock frequencies up to 100 MHz (6.5ns access time) • • • • • Two independent clocked FIFOs buffering data in opposite ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 DESCRIPTION The IDT72V3684/72V3694/72V36104 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 Each Mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Two ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/O AEA Port A Almost- O Empty Flag AEB ...
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... FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB. ...
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... MHZ O ) vs. Clock Frequency ( COMMERCIAL TEMPERATURE RANGE Commercial –0.5 to +4.6 –0 +0.5 CC –0 +0.5 CC ±20 ±50 ±50 ±400 –65 to 150 IDT72V3684 IDT72V3694 IDT72V36104 Commercial (2) CLK Min. Typ. Max. 2.4 — — — — 0.5 — — ± — — ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken ...
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... IDT72V3684L15 IDT72V3694L15 IDT72V36104L15 Min. Max. Unit — 66.7 MHz 15 — — — — ns 4.5 — ns 4.5 — — ns 7.5 — ns 7.5 — — — ...
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... IDT72V3684L10 IDT72V3694L10 IDT72V36104L10 Min. Max. 2 6.5 2 6.5 1 6.5 1 6.5 1 6.5 0 6.5 (1) and CLKB↑ 6 COMMERCIAL TEMPERATURE RANGE = 30pF L IDT72V3684L15 IDT72V3694L15 IDT72V36104L15 Min. Max. Unit ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 SIGNAL DESCRIPTION MASTER RESET (MRS1, MRS2) After power up, a Master Reset operation must be performed by providing ...
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... The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 16,380 for the IDT72V3684 32,764 for the IDT72V3694; and 1 to 65,532 for the IDT72V36104. After all the offset registers are MRS1 MRS2 X1 AND Y1 REGlSTERS ↑ ...
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... IDT72V3684, IDT72V3694, TM WITH or IDT72V36104, respectively. The four registers are written in the order Y1, X1, Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1 register and the last-bit write stores the least significant bit of the X2 register. Each register value can be programmed from 1 to 16,380 (IDT72V3684 32,764 (IDT72V3694 65,532 (IDT72V36104) ...
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... (X1+1) to [65,536-(Y1+1)] (65,536-Y1) to 65,535 32,768 65,536 (1,2) (3) (3) IDT72V36104 (X2+1) to [65,536-(Y2+1)] (65,536-Y2) to 65,535 32,768 65,536 The setup and hold time constraints to the port clocks for the port Chip Selects and Write/Read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs port enable is LOW during a clock cycle, the port’ ...
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... IDT72V3684, IDT72V3694, or IDT72V36104 respec- tively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [16,384-(Y+1)], [32,768-(Y+1)], or [65,536-(Y+1)] for the IDT72V3684, IDT72V3694, or IDT72V36104 respectively. Note that a data word present in the FIFO output register has been read from memory. 14 ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 BYTE ORDER ON PORT A: B35 B27 BYTE ORDER ON PORT SIZE X L ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLKA CLKB t RSTS MRS1 BE/FWFT FS2, FS1,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKA 1 4 MRS1, MRS2 t FSS t FSH FS2 t t FSS FSH FS1,FS0 0,0 FFA/IRA ENA ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLK t CLKH t CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKB FFB/IRB HIGH CSB W/RB MBB ENB B0-B17 DATA SIZE TABLE FOR WORD WRITES TO FIFO2 (1) SIZE ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (Standard Mode ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKB EFB/ORB HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode) t MDV ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLKA CSA LOW WRA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IRA HIGH t ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKA CSA LOW HIGH WRA t t ENS2 ENH MBA t t ENH ENS2 ENA FFA HIGH t ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH t ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENS2 ENH ENB FFB HIGH t ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB ORB HIGH ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA ORA HIGH ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH ...
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... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO Maximum FIFO Depth = 16,384 for the IDT72V3684, 32,768 for the IDT72V3694, 65,536 for the IDT72V36104. ...
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... FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO Maximum FIFO Depth = 16,384 for the IDT72V3684, 32,768 for the IDT72V3694, 65,536 for the IDT72V36104. ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKB CSB W/RB MBB ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA t EN A0-A35 FIFO2 Output Register ...
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... No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit setup procedure 16,384, 32,768 and 65,536 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively. Figure 29. Retransmit Timing for FIFO1 (IDT Standard Mode) ...
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... W1 = first word written to the FIFO2 after Master Reset on FIFO2 more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRB will be LOW throughout the Retransmit setup procedure 16,385, 32,769 and 65,537 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively. TM ...
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IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5 V Input Data, 1.5 V ...
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ORDERING INFORMATION IDT X XX XXXXXX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 10/31/2000 pgs and 36 12/14/2000 pgs. 4 and 5. 02/08/2001 pgs. 5 ...