ics9fg1201 Integrated Device Technology, ics9fg1201 Datasheet - Page 7

no-image

ics9fg1201

Manufacturer Part Number
ics9fg1201
Description
Frequency Generator For P4tm Cpu, Pci-express* & Fully Buffered Dimm Clocks
Manufacturer
Integrated Device Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ics9fg1201CGLF
Manufacturer:
ICS
Quantity:
20 000
Part Number:
ics9fg1201HFLF
Manufacturer:
IDT
Quantity:
872
Part Number:
ics9fg1201HGLFT
Manufacturer:
IDT
Quantity:
900
* Note: See SMBus Address Mapping (page 6), for programming SMBus Read/Write Address
IDT
ICS9FG1201H
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
TM
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D0
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
/ICS
Byte N + X -1
WR
P
T
TM
Beginning Byte N
Data Byte Count = X
Index Block Write Operation
Slave Address D0
Beginning Byte = N
Byte N + X - 1
Controller (Host)
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
General SMBus serial interface information for the ICS9FG1201H
starT bit
stoP bit
WRite
(h)
*
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
(h)
7
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D0
• ICS clock will acknowledge
• Controller (host) sends the begining byte
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D1
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
location = N
was written to byte 8)
WR
RD
RT
N
P
T
Slave Address D0
Slave Address D1
Index Block Read Operation
Beginning Byte = N
Controller (Host)
Not acknowledge
ACK
ACK
Repeat starT
starT bit
stoP bit
WRite
ReaD
(h)
(h)
*
*
.
ICS (Slave/Receiver)
Data Byte Count = X
Beginning Byte N
Byte N + X - 1
ACK
ACK
ACK
1371C — 02/12/08
(h)
(h)
(h)

Related parts for ics9fg1201