ics9fg1201 Integrated Device Technology, ics9fg1201 Datasheet - Page 3

• Manufacturer Part Number: ics9fg1201
• Description: Frequency Generator For P4tm Cpu, Pci-express* & Fully Buffered Dimm Clocks
• Manufacturer: Integrated Device Technology

Power Groups
Pin Description
IDT
11,22,38,50 12,23,37,49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin # Pin Name
ICS9FG1201H
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
TM
VDD
/ICS
56
Pin Number
HIGH_BW#
CLK_IN
CLK_IN#
SMB_A0
OE0#
DIF_0
DIF_0#
OE1#
DIF_1
DIF_1#
VDD
GND
DIF_2
DIF_2#
OE2#
DIF_3
DIF_3#
OE3#
DIF_4
DIF_4#
OE4#
VDD
GND
DIF_5
DIF_5#
OE5#
SMB_A1
SMBDAT
TM
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
GND
55
Main PLL, Analog
Description
DIF clocks
Type
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Pin Description
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Input for reference clock.
"Complementary" reference clock input.
SMBus address bit 0 (LSB)
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
SMBus address bit 1
Data pin of SMBUS circuitry, 5V tolerant
3
1371C — 02/12/08