ST92E163-EPB/US STMicroelectronics, ST92E163-EPB/US Datasheet - Page 79

• Manufacturer Part Number: ST92E163-EPB/US
• Description: KIT DEMO MASS STORAGE
• Manufacturer: STMicroelectronics
• Type: Microcontroller Programmerr

Specifications of ST92E163-EPB/US

• Contents: Programmer, Cable, Power Supply, Software, Manual and more
• For Use With/related Products: ST9 MCUs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK MANAGEMENT (Cont’d)
5.3.4 Low Power Modes
The user can select an automatic slowdown of
clock frequency during Wait for Interrupt opera-
tion, thus idling in low power mode while waiting
for an interrupt. In WFI operation the clock to the
CPU core (CPUCLK) is stopped, thus suspending
program execution, while the clock to the peripher-
als (INTCLK) may be programmed as described in
the following paragraphs. An example of Low
Power operation in WFI is illustrated in
If low power operation during WFI is disabled
(LPOWFI bit = 0 in the CLKCTL Register), the
CPU CLK is stopped but INTCLK is unchanged.
If low power operation during Wait for Interrupt is
enabled (LPOWFI bit = 1 in the CLKCTL Register),
as soon as the CPU executes the WFI instruction,
the PLL is turned off and the system clock will be
forced to CLOCK2 divided by 16, or to CK_AF, if
this has been selected by setting WFI_CKSEL,
and providing CKAF_ST is set, thus indicating that
the internal RC oscillator is selected.
If the external clock source is used, the crystal os-
cillator may be stopped by setting the XTSTOP bit,
providing that the CK_AK clock is present and se-
lected, indicated by CKAF_ST being set. The crys-
tal oscillator will be stopped automatically on en-
tering WFI if the WFI_CKSEL bit has been set. It
Table 13. Summary of Operating Modes using main Crystal Controlled Oscillator
LOW POWER
INTERRUPT
INTERRUPT
PLL x BY 14
PLL x BY 10
PLL x BY 8
PLL x BY 6
WAIT FOR
WAIT FOR
SLOW 1
SLOW 2
RESET
MODE
XTAL/32
XTAL/32
INTCLK
x (14/D)
x (10/D)
XTAL/2
XTAL/2
XTAL/2
XTAL/2
XTAL/2
XTAL/2
x (8/D)
x (6/D)
If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.
INTCLK/N
INTCLK/N
INTCLK/N
INTCLK/N
INTCLK/N
INTCLK/N
CPUCLK
INTCLK
STOP
ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure
DIV2 PRS0-2 CSU_CKSEL MX0-1 DX2-0 LPOWFI XT_DIV16
1
1
1
1
1
1
1
1
38.
N-1
N-1
N-1
N-1
N-1
N-1
X
0
should be noted that selecting a non-existent
CK_AF clock source is impossible, since such a
selection requires that the auxiliary clock source
be actually present and selected. In no event can
a non-existent clock source be selected inadvert-
ently.
It is up to the user program to switch back to a fast-
er clock on the occurrence of an interrupt, taking
care to respect the oscillator and PLL stabilisation
delays, as appropriate.It should be noted that any
of the low power modes may also be selected ex-
plicitly by the user program even when not in Wait
for Interrupt mode, by setting the appropriate bits.
5.3.5 Interrupt Generation
System clock selection modifies the CLKCTL and
CLK_FLAG registers.
The clock control unit generates an external inter-
rupt request when CK_AF and CLOCK2/16 are
selected or deselected as system clock source, as
well as when the system clock restarts after a
hardware stop (when the STOP MODE feature is
available on the specific device). This interrupt can
be masked by resetting the INT_SEL bit in the
CLKCTL register. In the RCCU the interrupt is
generated with a high to low transition (see inter-
rupt and DMA chapters for further information).
1
1
1
1
X
X
X
0
1 0
0 0
1 1
0 1
00
X
X
X
111
111
D-1
D-1
D-1
D-1
X
X
X
X
X
X
X
X
1
0
1
1
1
1
1
0
1
1
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