ST92E163-EPB/US STMicroelectronics, ST92E163-EPB/US Datasheet
ST92E163-EPB/US
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ST92E163-EPB/US Summary of contents
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FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I Internal Memories: 20 Kbytes ROM/EPROM/ ■ OTP, 2 Kbytes RAM Register oriented 8/16 bit core ■ 224 general purpose registers available as ■ RAM, ...
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ST92163R4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Serial Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST92163R4 - GENERAL DESCRIPTION 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST9216x family brings the enhanced ST9 reg- ister-based architecture to a new range of high- performance microcontrollers specifically de- signed for USB (Universal Serial Bus) applica- tions. Their performance derives ...
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INTRODUCTION (Cont’d) Figure 1. Maximum Operating Frequency (f MAX FREQUENCY (MHz 2.5 Notes: 1) This mode is supported by 16-MHz Low Voltage devices only 2) This mode is supported by 8-MHz Low Voltage ...
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ST92163R4 - GENERAL DESCRIPTION INTRODUCTION (Cont’d) Figure 2. ST92163 Architectural Block Diagram 20K ROM/ EPROM/OTP 2K RAM DMA USBGND USB USBVCC with 16 end- USBDM0 points USBDP0 USBOE 5V/3.3V USBSOF Voltage Regulator 256 bytes Register File 8/16-bit CPU Interrupt INT[7:0] ...
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INTRODUCTION (Cont’d) 1.1.1 Core Architecture The nucleus of the ST92163 is the enhanced ST9 Core that includes the Central Processing Unit (CPU), the register file, the interrupt and DMA con- troller, and the Memory Management Unit (MMU). Three independent buses ...
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ST92163R4 - GENERAL DESCRIPTION INTRODUCTION (Cont’d) 1.1.5 On-chip Peripherals USB Interface The USB interface provides a full speed USB 1.1 compliant port with embedded transceiver and voltage regulator endpoints are available supporting USB devices. ...
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PIN DESCRIPTION Figure 3. 64-Pin Package Pin-Out WKUP14/A10/P1.2 1 WKUP14/A9/P1.1 WKUP14/A8/P1.0 D7/A7/P0.7 D6/A6/P0.6 D5/A5/P0.5 D4/A4/P0.4 D3/A3/P0.3 D2/A2/P0.2 D1/A1/P0.1 D0/A0/P0.0 AIN5/P6.7 AIN4/P6.6 USBSOF/AIN3/P6.5 USBSOF/AIN2/P6.4 XTOUT/WKUP13/AIN1/P6 N.C. = Not connected ST92163R4 - GENERAL DESCRIPTION 64 48 N.C. USBVCC USBGND ...
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ST92163R4 - GENERAL DESCRIPTION Figure 4. 56-Pin Package Pin-Out WKUP3/RXCLK/INT7/P3.3 WKUP2/CLKOUT/TXCLK/INT7/P3.2 WKUP1/RTS/INT7/P3.1 WKUP0/SOUT/INT7/P3.0 WKUP14/A15/P1.7 WKUP14/A14/P1.6 WKUP14/A13/P1.5 WKUP14/A12/P1.4 WKUP14/A11/P1.3 WKUP14/A10/P1.2 WKUP14/A9/P1.1 WKUP14/A8/P1.0 Note: ST92163 devices in DIP56 are available for development purposes. Table 1. Power Supply Pins Name Function Main Power ...
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I/O PORT PINS All the ports of the device can be programmed as Input/Output or in Input mode, compatible with TTL or CMOS levels (except where Schmitt Trig- ger is present). Each bit can be programmed indi- vidually (Refer ...
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ST92163R4 - GENERAL DESCRIPTION Table 4. ST92163 Alternate Functions Pin No. Port General Purpose I/O Name P0 A0/D0 P0 A1/ P0.7 ...
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Pin No. Port General Purpose I/O Name All ports useable for general pur- P3 pose I/O (input, output or bidirec- tional P4.0 13 ...
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ST92163R4 - GENERAL DESCRIPTION Pin No. Port General Purpose I/O Name INT3 All ports useable for general pur- pose ...
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Pin No. Port General Purpose I/O Name P6 P6 AIN3 All ports useable for general pur- pose I/O (input, output or bidirec- P6 tional) P6 *Eight interrupt lines internally connected to INT7 ...
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ST92163R4 - GENERAL DESCRIPTION How to configure the I/O ports To configure the I/O ports, use the information in Table 3 and Table 4 and the Port Bit Configuration Table in the I/O Ports Chapter on I/O Note = the ...
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MEMORY MAP Figure 5. ST92163 Memory Map SEGMENT 21h 20FFFFh Internal RAM 2 Kbytes 20F800h SEGMENT 20h Note: Internal RAM addresses are repeated each 2 Kbytes inside segment 20h. 004FFFh Internal ROM/EPROM 20 Kbytes 000000h Note: The total amount ...
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ST92163R4 - GENERAL DESCRIPTION 1.5 ST92163 REGISTER MAP Table 6 contains the map of the group F peripheral pages. The common registers used by each peripheral are listed in Table 5. Be very careful to correctly program both: – The ...
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Table 6. Group F Pages Register Map Resources available on the ST92163 device: Register R255 Res. R254 Res. Res. Port R253 3 R252 WCR R251 R250 Port WDT 6 R249 R248 R247 Res. R246 Res. Port R245 ...
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ST92163R4 - GENERAL DESCRIPTION Table 7. Detailed Register Map Page Reg. Register Block No. No. R227 I/O R228 Port 3:5 R229 R230 R231 R232 System R233 R234 Core R235 MODER R236 R237 R238 R239 R242 R243 R244 INT R245 R246 ...
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Page Reg. Register Block No. No. Name R240 EP0RA R241 EP0RB R242 EP1RA R243 EP1RB R244 EP2RA R245 EP2RB R246 EP3RA R247 EP3RB 4 R248 EP4RA R249 EP4RB R250 EP5RA R251 EP5RB R252 EP6RA R253 EP6RB R254 EP7RA USB R255 ...
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ST92163R4 - GENERAL DESCRIPTION Page Reg. Register Block No. No. R240 REG0HR R241 REG0LR R242 REG1HR R243 REG1LR R244 CMP0HR R245 CMP0LR R246 CMP1HR R247 CMP1LR 10 MFT R248 R249 R250 R251 R252 R253 R254 T_FLAGR R255 R240 DADDR0 R241 ...
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Page Reg. Register Block No. No. Name R240 I2CCR R241 I2CSR1 R242 I2CSR2 R243 I2CCCR R244 I2COAR1 R245 I2COAR2 R246 I2CDR R247 I2CADR 20 I2C R248 I2CISR R249 I2CIVR R250 I2CRDAP R251 I2CRDC R252 I2CTDAP R253 I2CTDC R254 I2CECCR R255 ...
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ST92163R4 - GENERAL DESCRIPTION Page Reg. Register Block No. No. R248 I/O R249 Port R250 8 R251 43 R252 I/O R253 Port R254 9 R255 R240 CLKCTL 55 RCCU R242 CLK_FLAG R246 PLLCONF R249 WUCTRL R250 WUMRH R251 WUMRL 59 ...
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DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 address- ing ...
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ST92163R4 - DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) Figure 8. Register Groups 255 F PAGED REGISTERS 240 239 E SYSTEM REGISTERS 224 223 Figure ...
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MEMORY SPACES (Cont’d) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus R231, RE7h and R11100111b represent the ...
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ST92163R4 - DEVICE ARCHITECTURE 2.3 SYSTEM REGISTERS The System registers are listed in are used to perform all the important system set- tings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a ...
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SYSTEM REGISTERS (Cont’d) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt ...
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ST92163R4 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a ...
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SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 RG4 RG3 RG2 RG1 RG0 Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range ...
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ST92163R4 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) Figure 11. Pointing to a single group of 16 registers REGISTER GROUP BLOCK NUMBER REGISTER FILE ...
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SYSTEM REGISTERS (Cont’d) 2.3.4 Paged Registers pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the ...
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ST92163R4 - DEVICE ARCHITECTURE Note: Setting the HIMP bit is recommended for noise reduction when only internal Memory is used. If the memory access ports are declared as an ad- dress AND as an I/O port (for example: P10... P14 ...
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SYSTEM REGISTERS (Cont’d) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined 7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write Register Group: E (System) ...
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ST92163R4 - DEVICE ARCHITECTURE 2.4 MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a ...
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MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to per- form memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR ...
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ST92163R4 - DEVICE ARCHITECTURE 2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address ...
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ADDRESS SPACE EXTENSION (Cont’d) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program mem- ory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ...
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ST92163R4 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 DPR0 DPR0 DPR0 DPR0 DPR0 ...
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MMU REGISTERS (Cont’d) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruc- tion has been executed (or ldpp, ...
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ST92163R4 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) Figure 18. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR 44/230 4M bytes 16K 16K 16K 64K 64K 16K 64K 3FFFFFh 294000h 240000h 23FFFFh 20C000h 200000h 1FFFFFh 040000h 03FFFFh 030000h ...
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MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, ...
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ST92163R4 - INTERRUPTS 3 INTERRUPTS 3.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current pro- gram execution can be suspended to allow the ST9 to execute a specific response routine when such an event ...
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INTERRUPTS (Cont’d) 3.2 INTERRUPT VECTORING The ST9 implements an interrupt vectoring struc- ture which allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine automatically. When an interrupt request is acknowledged, the peripheral ...
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ST92163R4 - INTERRUPTS INTERRUPTS (Cont’d) 3.2.2 Segment Paging Routines The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compati- bility mode and ST9+ interrupt management mode. ST9 backward compatibility mode (ENCSR = 0) ...
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Table 10. Table 10. Daisy Chain Priority Highest Position INTA0 INTA1 INTB0 INTB1 INTC0 INTC1 INTD0 INTD1 USB MFT SCI Lowest Position I2C 3.4.4 Dynamic Priority Level Modification The main ...
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ST92163R4 - INTERRUPTS ARBITRATION MODES (Cont’d) Examples In the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. Figure 22. Simple Example of a Sequence ...
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ARBITRATION MODES (Cont’d) Example 2 In the second example, (more complex, 23), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher ...
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ST92163R4 - INTERRUPTS ARBITRATION MODES (Cont’d) 3.5.2 Nested Mode The difference between Nested mode and Con- current mode, lies in the modification of the Cur- rent Priority Level (CPL) during interrupt process- ing. The arbitration phase is basically identical to ...
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ARBITRATION MODES (Cont’d) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – The PC high ...
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ST92163R4 - INTERRUPTS 3.6 EXTERNAL INTERRUPTS The standard ST9 core contains 8 external inter- rupts sources grouped into four pairs. INT7 is connected to 8 different I/O pins of Port 3. Once these pins are programmed as alternate function they ...
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EXTERNAL INTERRUPTS (Cont’d) Figure 27. External Interrupts Control Bits and Vectors Watchdog/Timer End of count TEA0 INT 0 pin TEA1 ADC INT 1 pin INT 2 pin INT 3 pin INT 4 pin INT 5 pin RCCU TED0 INT 6 ...
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ST92163R4 - INTERRUPTS 3.7 MANAGEMENT OF WAKE-UP LINES AND EXTERNAL INTERRUPT LINES In the ST92163, fifteen (WKUP[14:0]) are available on external pins. The WKUP[15] line is internally connected to the USB interface line. Figure 28. Wake-Up Lines and External Interrupt ...
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TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is high ...
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ST92163R4 - INTERRUPTS 3.10 INTERRUPT RESPONSE TIME The interrupt arbitration protocol functions com- pletely asynchronously from instruction flow, and requires 6 CPUCLK cycles to resolve the request’s priority. Requests are sampled every 5 CPUCLK cycles. If the interrupt request comes ...
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INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Page: System Reset value: 1000 0111 (87h) 7 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit enables the 16-bit ...
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ST92163R4 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) 7 IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0 Bit 7 = IPD1: INTD1 Interrupt Pending bit Bit ...
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INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110 (x6h TLTEV TLIS IAOS EWEN Bits 7:4 = V[7:4]: Most significant nibble of Exter- nal Interrupt Vector. ...
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ST92163R4 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh ENCSR Bits 7, 5:0 = Reserved, keep in reset state. Refer to the ...
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) 3.12.1 Introduction The Wake-up/Interrupt Management Unit extends the number of external interrupt lines from (depending on the number of external interrupt lines mapped on external pins of the device). ...
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ST92163R4 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 3.12.3 Functional Description 3.12.3.1 Interrupt Mode To configure the 16 wake-up lines as interrupt sources, use the following procedure: 1. Configure the mask bits of the 16 wake-up lines (WUMRL, ...
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) Case 3: A wake-up event on the external wake- up lines occurs during the STOP bit setting se- quence There are two possible cases: 1. Interrupt requests to the CPU are disabled: in ...
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ST92163R4 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 3.12.4 Programming Considerations The following paragraphs give some guidelines for designing an application program. 3.12.4.1 Procedure for Entering/Exiting STOP mode 1. Program the polarity of the trigger event of external ...
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 3.12.5 Register Description WAKE-UP CONTROL REGISTER (WUCTRL) R249 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h STOP Bit 2 = STOP: Stop bit. To enter ...
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ST92163R4 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP MASK REGISTER HIGH (WUMRH) R250 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) 7 WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 Bit 7:0 = WUM[15:8]: Wake-Up Mask ...
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP TRIGGER REGISTER (WUTRH) R252 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) 7 WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity Bits These bits ...
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ST92163R4 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 4 ON-CHIP DIRECT MEMORY ACCESS (DMA) 4.1 INTRODUCTION The ST9 includes on-chip Direct Memory Access (DMA) in order to provide high-speed data transfer between peripherals and memory or Register File. Multi-channel DMA is ...
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DMA TRANSACTIONS The purpose of an on-chip DMA channel is to transfer a block of data between a peripheral and the Register File, or Memory. Each DMA transfer consists of three operations: – A load from/to the peripheral data ...
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ST92163R4 - ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d) When selecting the DMA transaction with memory, bit DCPR.RM (bit 0 of DCPR) must be cleared. To select between using the ISR or the DMASR reg- ister to extend the ...
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DMA TRANSACTIONS (Cont’d) 4.4 DMA CYCLE TIME The interrupt and DMA arbitration protocol func- tions completely asynchronously from instruction flow. Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their priority al- lows it. A DMA transfer ...
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ST92163R4 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 4.6 DMA REGISTERS As each peripheral DMA channel has its own spe- cific control registers, the following register list should be considered as a general example. The names and register bit allocations shown ...
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RESET AND CLOCK CONTROL UNIT (RCCU) 5.1 INTRODUCTION The Reset and Clock Control Unit (RCCU) com- prises two distinct sections: – the Clock Control Unit, which generates and manages the internal clock signals. – the Reset/Stop Manager, which detects ...
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ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 35. ST92163 Clock Distribution Diagram A/D 1...256 MFT P6.2 USB INTERFACE P6.3 8 MHz XTOUT DIV2=0 8 MHz Quartz 0 Oscillator 1 /2 RCCU 1/16 Internal RC oscillator 76/230 1/3 (TxINA/TxINB) ...
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CLOCK MANAGEMENT The various programmable features and operating modes of the CCU are handled by four registers: – MODER (Mode Register) This is a System Register (R235, Group E). The input clock divide-by-two and the CPU clock prescaler factors ...
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ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK MANAGEMENT (Cont’d) 5.3.1 PLL Clock Multiplier Programming The CLOCK1 signal generated by the oscillator drives a programmable divide-by-two circuit. If the DIV2 control bit in MODER is set (Reset Condi- tion), ...
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CLOCK MANAGEMENT (Cont’d) 5.3.4 Low Power Modes The user can select an automatic slowdown of clock frequency during Wait for Interrupt opera- tion, thus idling in low power mode while waiting for an interrupt. In WFI operation the clock to ...
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ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 38. Example of Low Power Mode programming PROGRAM FLOW XTSTOP = 0 CSU_CKSEL = 0 MX(1: DX2-0 ← 001 WAIT CSU_CKSEL Wait for the WFI_CKSEL ← 1 PLL locking ...
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CLOCK CONTROL REGISTERS MODE REGISTER (MODER) R235 - Read/Write System Register Reset Value: 1110 0000 (E0h DIV2 PRS2 PRS1 *Note: This register contains bits which relate to other functions; these are described in the chapter dealing ...
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ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTERS CLOCK FLAG REGISTER (CLK_FLAG) R242 -Read/Write Register Page: 55 Reset Value: 0100 1000 after a Watchdog Reset Reset Value: 0010 1000 after a Software Reset Reset Value: 0000 1000 ...
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PLL CONFIGURATION REGISTER (PLLCONF) R246 - Read/Write Register Page: 55 Reset Value: xx00 x111 MX1 MX0 - Bit 7:6 = Reserved. Bit 5:4 = MX[1:0]: PLL Multiplication Factor. Refer to Table 14 for multiplier settings. Bit 3 ...
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ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 40. RCCU Timing during STOP (CK_AF System Clock) STOP pin Xtal clock RC osc clock INTCLK ((N-1)*512+510 (**) Xtal Exit from RESET (*) if DIV2 =1 (**) +/- 1 ...
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OSCILLATOR CHARACTERISTICS The oscillator circuit uses an inverting gate circuit with tri-state output. Notes: Owing to the Q factor required, Ceramic Resonators may not provide a reliable oscillator source. OSCOUT must not be directly used to drive exter- nal ...
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ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU) 5.6 RESET/STOP MANAGER The Reset/Stop Manager resets the MCU when one of the three following events occurs: – A Hardware reset, initiated by a low level on the Reset pin. – A ...
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RESET/STOP MANAGER (Cont’d) The on-chip Timer/Watchdog generates a reset condition if the Watchdog mode is enabled (WCR.WDEN cleared, R252 page 0), and if the programmed period elapses without the specific code (AAh, 55h) written to the appropriate register. The RESET ...
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ST92163R4 - RESET AND CLOCK CONTROL UNIT (RCCU) 5.8 LOW VOLTAGE DETECTOR (LVD) RESET The on-chip Low Voltage Detector (LVD) gener- ates LVDRESET when the supply voltage drops below a reference value (brown-out protection). The reference value for the voltage ...
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LOW VOLTAGE DETECTOR (LVD) RESET (Cont’d) Figure 49 gives an example of an external Power On Reset circuit for power supplies with very slow power on ramp. Figure 49. Suggested External POR Circuit for applications with very slow V V ...
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ST92163R4 - EXTERNAL MEMORY INTERFACE (EXTMI) 6 EXTERNAL MEMORY INTERFACE (EXTMI) 6.1 INTRODUCTION The ST9 External Memory Interface uses two reg- isters (EMR1 and EMR2) to configure external memory accesses. Some interface signals are also affected by WCR - R252 ...
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EXTERNAL MEMORY SIGNALS The access to external memory is made using at least AS, DS, Port 0 and Port 1. RW, DS2, BREQ, BACK and WAIT signals improve functionality but are not always present on ST9 devices. Refer to ...
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ST92163R4 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) Figure 52. External memory Read/Write with and without a programmable wait n NO WAIT CYCLE T1 SYSTEM CLOCK AS (MC=0) ALE (MC=1) P1 ADDRESS DS (MC=0) P0 ADDRESS MULTIPLEXED RW ...
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EXTERNAL MEMORY SIGNALS (Cont’d) Figure 53. Effects of DS2EN on the behavior of DS and DS2 n SYSTEM CLOCK AS (MC=0) DS2EN=0 OR (DS2EN=1 AND UPPER MEMORY ADDRESSED): DS (MC=0) DS (MC=1, READ) DS (MC=1, WRITE) DS2 DS2EN=1 AND LOWER ...
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ST92163R4 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) 6.2.4 RW: Read/Write RW (Alternate Function Output, Active low, Tristate) identifies the type of memory cycle: RW=”1” identifies a memory read cycle, RW=”0” identifies a memory write cycle ...
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EXTERNAL MEMORY SIGNALS (Cont’d) Whenever it is sampled low, the System Clock is stretched and the external memory signals (AS, DS, DS2, RW, P0 and P1) are released in high-im- pedance. The external memory interface pins are driven again by ...
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ST92163R4 - EXTERNAL MEMORY INTERFACE (EXTMI) 6.3 REGISTER DESCRIPTION EXTERNAL MEMORY REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h DS2EN ASAF x Bit 7 = Reserved. Bit 6 = MC: Mode ...
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REGISTER DESCRIPTION (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0001 1111 (1Fh) 7 MEM - ENCSR DPRREM LAS1 SEL Bit 7 = Reserved. Bit 6 = ENCSR: Enable Code Segment Register. This bit ...
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ST92163R4 - EXTERNAL MEMORY INTERFACE (EXTMI) REGISTER DESCRIPTION (Cont’d) Bit 1:0 = UAS[1:0]: Upper memory address strobe stretch. These two bits contain the number of wait cycles (from add to the System Clock to stretch AS ...
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I/O PORTS 7.1 INTRODUCTION ST9 devices feature flexible individually program- mable multifunctional input/output lines. Refer to the Pin Description Chapter for specific pin alloca- tions. These lines, which are logically grouped as 8-bit ports, can be individually programmed to ...
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ST92163R4 - I/O PORTS PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 ...
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INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 57. Control Bits Bit 7 PxC2 PxC27 PxC1 PxC17 PxC0 PxC07 n Table 18. Port Bit Configuration Table ( 1... port number) PXC2n 0 PXC1n 0 PXC0n 0 PXn Configuration ...
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ST92163R4 - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 58. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 59. Input ...
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INPUT/OUTPUT BIT CONFIGURATION (Cont’d) When Px.n is programmed as an Output: (Figure 60) – The Output Buffer is turned Open-drain or Push-pull configuration. – The data stored in the Output Master Latch is copied both into the ...
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ST92163R4 - ALTERNATE FUNCTION ARCHITECTURE 7.5 ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output 7.5.1 Pin Declared as I/O A ...
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ON-CHIP PERIPHERALS 8.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic descrip- tion of the WDT peripheral. However depending on the ST9 device, some or all of WDT interface signals described may not be connected to exter- nal ...
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ST92163R4 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 8.1.2 Functional Description 8.1.2.1 External Signals The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to page 107. The WDIN Input pin can be used in one of four modes: ...
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TIMER/WATCHDOG (Cont’d) 8.1.2.7 Gated Input Mode This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When the input ...
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ST92163R4 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 8.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the ...
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TIMER/WATCHDOG (Cont’d) 8.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is ena- bled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 se- lection bit) and TLIS (EIVR.2, Top Level Input ...
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ST92163R4 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 8.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog ...
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TIMER/WATCHDOG (Cont’d) Bit 3 = INEN: Input Enable. This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and cleared by software. 0: The ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) 8.2 MULTIFUNCTION TIMER (MFT) 8.2.1 Introduction The Multifunction Timer (MFT) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic PWM generation and frequency measurement. The MFT comprises a 16-bit Up/Down counter ...
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MULTIFUNCTION TIMER (Cont’d) The configuration of each input is programmed in the Input Control Register. Each of the two output pins can be driven from any of three possible sources: – Compare Register 0 logic – Compare Register 1 logic ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 8.2.2 Functional Description The MFT operating modes are selected by pro- gramming the Timer Control Register (TCR) and the Timer Mode Register (TMR). 8.2.2.1 Trigger Events A trigger event may be generated ...
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MULTIFUNCTION TIMER (Cont’d) 8.2.2.8 Free Running Mode The timer counts continuously ( Down mode) and the counter value simply overflows or underflows through FFFFh or zero; there is no End Of Count condition as such, and no reloading ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) Every software or external trigger event on REG0R performs a reload from REG0R resetting the Biload cycle. In One Shot mode (reload initiat software external trigger), reloading ...
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MULTIFUNCTION TIMER (Cont’d) 8.2.3 Input Pin Assignment The two external inputs (TxINA and TxINB) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both rising and falling edges) by ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 8.2.3.1 TxINA = I/O - TxINB = I/O Input pins A and B are not used by the Timer. The counter clock is internally generated and the up/ down selection may be ...
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MULTIFUNCTION TIMER (Cont’d) 8.2.3.9 TxINA = Clock Up - TxINB = Clock Down The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock and the up/down control are ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 8.2.3.13 Autodiscrimination Mode The phase between two pulses (respectively on in- put pin B and input pin A) generates a one step up (or down) count, so that the up/down control and ...
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MULTIFUNCTION TIMER (Cont’d) 8.2.4 Output Pin Assignment Two external outputs are available when pro- grammed as Alternate Function Outputs of the I/O pins. Two registers Output A Control Register (OACR) and Output B Control Register (OBCR) define the driver for ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by the Over/Underflow and by Compare 1. OACR is programmed with TxOUTA preset to ...
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MULTIFUNCTION TIMER (Cont’d) 8.2.5 Interrupt and DMA 8.2.5.1 Timer Interrupt The timer has 5 different Interrupt sources, be- longing to 3 independent groups, which are as- signed to the following Interrupt vectors: Table 22. Timer Interrupt Structure Interrupt Source COMP ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) Figure 71. Pointer Mapping for Register to Register Transfers Register File 8 bit Counter XXXXXX11 8 bit Addr Pointer XXXXXX10 8 bit Counter XXXXXX01 8 bit Addr Pointer XXXXXX00 8.2.5.4 DMA Transaction ...
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MULTIFUNCTION TIMER (Cont’d) 8.2.5.6 DMA End Of Block Interrupt Routine An interrupt request is generated after each block transfer (EOB) and its priority is the same as that assigned in the usual interrupt request, for the two channels ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) CAPTURE LOAD 0 HIGH REGISTER (REG0HR) R240 - Read/Write Register Page: 10 Reset value: undefined 7 R15 R14 R13 R12 R11 This register is used to capture values from the Up/Down counter ...
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MULTIFUNCTION TIMER (Cont’d) TIMER CONTROL REGISTER (TCR) R248 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CEN CCP0 CCMP0 CCL UDC UDCS OF0 CS Bit 7 = CEN: Counter enable. This bit is ANDed with the Global ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) TIMER MODE REGISTER (TMR) R249 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 OE1 OE0 BM RM1 RM0 ECK REN Bit 7 = OE1: Output 1 enable. 0: Disable ...
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MULTIFUNCTION TIMER (Cont’d) EXTERNAL INPUT CONTROL (T_ICR) R250 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 IN3 IN2 IN1 IN0 A0 Bits 7:4 = IN[3:0]: Input pin function. These bits are set and cleared by software. TxINA ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) OUTPUT A CONTROL REGISTER (OACR) R252 - Read/Write Register Page: 10 Reset value: 0000 0000 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P Bits 7:6 = C0E[0:1]: COMP0 action bits. These ...
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MULTIFUNCTION TIMER (Cont’d) OUTPUT B CONTROL REGISTER (OBCR) R253 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 OEV 0P Bits 7:6 = C0E[0:1]: COMP0 Action Bits. These bits are set and ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) FLAG REGISTER (T_FLAGR) R254 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CP0 CP1 CM0 CM1 OUF Bit 7 = CP0: Capture 0 flag. This bit is set by ...
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MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA MASK REGISTER (IDMR) R255 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 GTIEN CP0D CP0I CP1I CM0D CM0I CM1I OUI Bit 7 = GTIEN: Global timer interrupt enable. This bit is set and ...
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ST92163R4 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) DMA ADDRESS POINTER REGISTER (DAPR) R241 - Read/Write Register Page: 9 Reset value: undefined 7 DAP7 DAP6 DAP5 DAP4 DAP3 DAP2 Bits 7:2 = DAP[7:2]: MSB of DMA address regis- ter location. ...
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MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA CONTROL REGISTER (IDCR) R243 - Read/Write Register Page: 9 Reset value: 1100 0111 (C7h) 7 CPE CME DCTS DCTD SWEN PL2 PL1 PL0 Bit 7 = CPE: Capture 0 EOB. This bit is set by hardware ...
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ST92163R4 - USB PERIPHERAL (USB) 8.3 USB PERIPHERAL (USB) 8.3.1 Introduction The USB Peripheral provides a full-speed function interface between the USB bus and the ST9 mi- crocontroller. 8.3.2 Main Features USB Specification Version 1.1 Compliant ■ Supports 8 device ...
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USB INTERFACE (Cont’d) 8.3.3.1 DMA transfer DMA descriptors for each endpoint, located in the ST9 register file, indicate where the related mem- ory buffer is located in RAM, how large the allocat- ed buffer is and how many bytes must ...
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ST92163R4 - USB PERIPHERAL (USB) Figure 73. DMA buffers and related register file locations R17 R16 R15 R14 R13 R12 Register File R11 R10 REGISTER FILE LOCATIONS 8.3.3.3 Interrupt modes ...
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USB INTERFACE (Cont’d) Procedure for entering Suspend Mode 1. Set the TIM_SUSP bit in the USBCTLR register (bit 6 of R252 in page 15) to suspend the digital part of the USB cell. 2. Clear both the Wake-up Pending Registers ...
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ST92163R4 - USB PERIPHERAL (USB) Example code for Entering Suspend Mode void Stop_MCU the loop to ensure the MCU goes to STOP do { spp(0); EIPR = 0x0;// Clear pending bits spp(15); CTLR |= CTR_TIM_SUSP;// Stop ...
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USB INTERFACE (Cont’d) 8.3.4 Register Description USB registers can be divided into three groups: – Common registers (page 15): interrupt registers and USB control registers. – Function and endpoint registers (pages 15, 4 and 5 depending on how many endpoints ...
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ST92163R4 - USB PERIPHERAL (USB) USB INTERFACE (Cont’d) Bit 0 = Reserved. This bit is fixed by hardware at 0. INTERRUPT STATUS REGISTER (USBISTR) R249 - Read/Write Register page: 15 Reset Value: 0000 0000 (00h DOVR ERR ESUSP ...
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USB INTERFACE (Cont’d) Bit 4 = ESUSP: End Suspend mode activity detected during Suspend mode 1: USB activity is detected that wakes up the USB interface during suspend mode. Note: This event asynchronously clears the LP_SUSP bit in ...
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ST92163R4 - USB PERIPHERAL (USB) USB INTERFACE (Cont’d) Interrupt sources are classified according to the following table CONTROL REGISTER (USBCTLR) R252 - Read/Write Register page: 15 Reset Value: 0001 0101 (15h) 7 TIM_ 0 0 SDNAV RESUME SUSP Bit 7 ...
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USB INTERFACE (Cont’d) CTR INTERRUPT FLAGS (CTRINF) R253 - Read/Write Register page: 15 Reset Value: 00xx xxx0 (xxh INTO ENID3 ENID2 ENID1 ENID0 Note: This register is used only when the SDNAV bit is 1. Bit 7:6 ...
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ST92163R4 - USB PERIPHERAL (USB) USB INTERFACE (Cont’d) DEVICE n ADDRESS (DADDRn) R240 to R247 - Read/Write Register page: 15 Reset Value: 0000 0000 (00h ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Note: This register is also reset ...
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USB INTERFACE (Cont’d) Bit 5:4 = STAT_TX [1:0] Status bits, for transmis- sion transfers. These bits contain the information about the end- point status, which are listed below: Table 27. Transmission status encoding STAT_TX Meaning [1:0] DISABLED: all transmission requests ...
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ST92163R4 - USB PERIPHERAL (USB) USB INTERFACE (Cont’d) ENDPOINT n REGISTER B (EPnRB) (RECEPTION) R241-R255 (odd) - Read/Write Register pages: 4 & 5 Reset value: 0000 0000 (00h) 7 ST_OU DTOG_ STAT_ STAT_ EnA3 T RX RX1 RX0 These registers ...
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USB INTERFACE (Cont’d) 8.3.4.3 Miscellaneous Registers These registers contain device configuration pa- rameters or optional functions of USB interface. DEVICE CONFIGURATION 1 (DEVCONF1) R244 - Read/Write Register page: 60 Reset value: 0000 1111 (0Fh) 7 USBOE LS_ ...
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ST92163R4 - USB PERIPHERAL (USB) USB INTERFACE (Cont’d) Bit 0 = SOFP_ENABLE: Start-Of-Frame Pulse Enable. Set by software to enable the use of the USBSOF alternate output function. 1: USBSOF alternate function enabled 0: USBSOF output disabled USBSOF outputs a ...
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USB INTERFACE (Cont’d) 8.3.5 Register pages summary The registers are located in different register file pages. To help finding the correct page for each Table 31. USB Register Page Mapping Address Page 4 240 (F0h) EP0RA 241 (F1h) EP0RB 242 ...
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ST92163R4 - USB PERIPHERAL (USB) Reg. Register 7 Name No. CTRINF 0 R253 Reset Value 0 FNRH RXDP R254 Reset Value 0 FNRL FN7 R255 Reset Value x 152/230 INTO ENID3 RXDM LCK ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) 8.4 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) 8.4.1 Introduction The Multiprotocol Serial Communications Inter- face (SCI-M) offers full-duplex serial data ex- change with a wide range of external equipment. The SCI-M offers four operating ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.3 Functional Description The SCI-M has four operating modes: – Asynchronous mode – Asynchronous mode with synchronous clock – Serial expansion mode – Synchronous mode Figure 75. SCI ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.4 SCI-M Operating Modes 8.4.4.1 Asynchronous Mode In this mode, data and clock can be asynchronous (the transmitter and receiver can use their own clocks to sample received ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.4.3 Serial Expansion Mode This mode is used to communicate with an exter- nal synchronous peripheral. The transmitter only provides the clock waveform during the period that data ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 77. SCI -M Operating Modes DATA I/O START BIT 16 16 CLOCK Asynchronous Mode I/O DATA START BIT (Dummy) CLOCK Serial Expansion Mode Note: In all operating ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.5 Serial Frame Format Characters sent or received by the SCI can have some or all of the features in the following format, depending on the operating mode: ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.5.1 Data transfer Data to be transmitted by the SCI is first loaded by the program into the Transmitter Buffer Register. The SCI will transfer the data into ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 79. Auto Echo Configuration TRANSMITTER RECEIVER All modes except Synchronous Figure 80. Loop Back Configuration LOGICAL 1 TRANSMITTER RECEIVER All modes except Synchronous Figure 81. Auto Echo ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.6 Clocks And Serial Transmission Rates The communication bit rate of the SCI transmitter and receiver sections can be provided from the in- ternal Baud Rate Generator or ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 34. SCI-M Baud Rate Generator Divider Values Example 1 Baud Clock Desired Freq Rate Factor 50. 75. 110. 300. ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.8 Input Signals SIN: Serial Data Input. This pin is the serial data input to the SCI receiver shift register. TXCLK: External Transmitter Clock Input. This pin is ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.10 Interrupts and DMA 8.4.10.1 Interrupts The SCI can generate interrupts as a result of sev- eral conditions. Receiver interrupts include data pending, receive errors (overrun, framing and ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 37. SCI-M Interrupt Vectors Interrupt Source Transmitter Buffer or Shift Register Empty Transmit DMA end of Block Received Data Pending Receive DMA end of Block Break Detector ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.10.2 DMA Two DMA channels are associated with the SCI, for transmit and for receive. These follow the reg- ister scheme as described in the DMA chapter. DMA ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 8.4.11 Register Description The SCI-M registers are located in the following pages in the ST9: SCI-M number 0: page 24 (18h) SCI-M number 1: page 25 (19h) (when ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER DMA COUNTER POINTER (RDCPR) R240 - Read/Write Reset value: undefined 7 RC7 RC6 RC5 RC4 RC3 Bit 7:1 = RC[7:1]: Receiver DMA Counter Pointer. These bits contain ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT VECTOR REGISTER (S_IVR) R244 - Read/Write Reset value: undefined Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad- dress. User programmable ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT MASK REGISTER (IMR) R246 - Read/Write Reset value: 0xx00000 7 BSN RXEOB TXEOB RXE RXA Bit 7 = BSN: Buffer or shift register empty inter- rupt. This ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT STATUS REGISTER (S_ISR) R247 - Read/Write Reset value: undefined RXAP RXBP RXDP TXBEM Bit 7 = OE: Overrun Error Pending. This bit is ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER BUFFER REGISTER (RXBR) R248 - Read only Reset value: undefined 7 RD7 RD6 RD5 RD4 RD3 Bit 7:0 = RD[7:0]: Received Data. This register stores the data ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT/DMA PRIORITY REGISTER (IDPR) R249 - Read/Write Reset value: undefined 7 AMEN SB SA RXD TXD PRL2 Bit 7 = AMEN: Address Mode Enable. This bit, together with ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) CHARACTER CONFIGURATION (CHCR) R250 - Read/Write Reset value: undefined PEN AB SB1 Bit 7 = AM: Address Mode. This bit, together with the AMEN bit ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) CLOCK CONFIGURATION REGISTER (CCR) R251 - Read/Write Reset value: 0000 0000 (00h) 7 XTCLK OCLK XRX XBRG CD AEN Bit 7 = XTCLK This bit, together with the ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) BAUD RATE GENERATOR HIGH REGISTER (BRGHR) R252 - Read/Write Reset value: undefined 15 BG15 BG14 BG13 BG12 BG11 BAUD RATE GENERATOR LOW REGISTER (BRGLR) R253 - Read/Write Reset ...
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ST92163R4 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) SYNCHRONOUS OUTPUT CONTROL (SOCR) R255 - Read/Write Reset value: 0000 0001 (01h) 7 OUTP OUTS OCKP OCKS RTSE Bit 7 = OUTPL: SOUT ...
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ST92163R4 - I2C BUS INTERFACE 2 8 BUS INTERFACE 8.5.1 Introduction 2 The I C bus Interface serves as an interface be- tween the microcontroller and the serial I provides both multimaster and slave functions with both 7-bit ...
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I C BUS INTERFACE (Cont’d) 2 Figure 85 Interface Block Diagram DATA SDA CONTROL CLOCK SCL CONTROL DMA 8.5.3 Functional Description Refer to the I2CCR, I2CSR1 and I2CSR2 registers in Section 8.5.7. for the bit definitions. 2 ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’d) The following seven registers are used to handle the interrupt and the DMA features: – Interrupt Status Register I2CISR – Interrupt Mask Register I2CIMR – Interrupt Vector Register I2CIVR ...
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I C BUS INTERFACE (Cont’d) 2 Figure 86 BUS Protocol SDA SCL START CONDITION Any transfer can be done using either the I registers directly or via the DMA. If the transfer done directly ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’d) Next, depending on the data direction bit (least significant bit of the address byte), and after the generation of an acknowledge, the slave must go in sending or receiving ...
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I C BUS INTERFACE (Cont’d) Then the slave address is sent to the SDA line. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the I2CSR1.EVF ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’d) Figure 87. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 ...
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EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, ADDTX=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’d) 8.5.5 Interrupt Features 2 The I Cbus interface has three interrupt sources related to “Error Condition”, “Peripheral Ready to Transmit” and “Data Received”. The peripheral uses the ST9+ interrupt ...
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I C BUS INTERFACE (Cont’d) Note: Until the pending bit is reset (while the cor- responding mask bit is set), the peripheral proc- esses an interrupt request. So the end of an interrupt routine the pending bit ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’d) 8.5.6.1 DMA between Peripheral and Register File If the DMA transaction is made between the pe- ripheral and the Register File, one register is required to hold the DMA ...
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I C BUS INTERFACE (Cont’d) 8.5.7 Register Description IMPORTANT guarantee correct operation, before enabling the peripheral (while I2CCR.PE=0), configure bit7 and bit6 of the I2COAR2 register according to the internal clock INTCLK (for example 11xxxxxxb in the ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’d) Bit 0 = ITE Interrupt Enable. The ITE bit enables the generation of interrupts. This bit is set and cleared by software and cleared by hardware when the interface ...
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I C BUS INTERFACE (Cont’d) – Address byte successfully transmitted in Mas- ter mode. (I2CSR1.EVF = 1 and I2CSR2.ADDTX=1) Bit 6 = ADD10 10-bit addressing in Master mode. This bit is set when the master has sent the first ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’ STATUS REGISTER 2 (I2CSR2) R242 - Read Only Register Page: 20 Reset Value: 0000 0000 (00h ADDTX AF STOPF ARLO BERR GCAL Note: ...
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I C BUS INTERFACE (Cont’ CLOCK CONTROL REGISTER (I2CCCR) R243 - Read / Write Register Page: 20 Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0 Bit 7 = FM/SM Fast/Standard ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’ OWN ADDRESS REGISTER 2 (I2COAR2) R245 - Read / Write Register Page: 20 Reset Value: 0000 0000 (00h) 7 FREQ1 FREQ0 EN10BIT FREQ2 0 Bits 7:6,4 ...
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I C BUS INTERFACE (Cont’d) INTERRUPT STATUS REGISTER (I2CISR) R248 - Read / Write Register Page: 20 Reset Value: 1xxx xxxx (xxh) 7 DMASTOP PRL2 PRL1 PRL0 0 Bit 7 = DMASTOP DMA suspended mode. This bit selects between ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’d) INTERRUPT VECTOR REGISTER (I2CIVR) R249 - Read / Write Register Page: 20 Reset Value: Undefined Bits 7:3 = V[7:3] Interrupt Vector Base Address. ...
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I C BUS INTERFACE (Cont’d) TRANSMITTER DMA SOURCE POINTER REGISTER (I2CTDAP) R252 - Read / Write Register Page: 20 Reset Value: Undefined 7 TA7 TA6 TA5 TA4 TA3 TA2 TA1 Bits 7:1= TA[7:1] Transmit DMA Address Pointer. I2CTDAP contains ...
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ST92163R4 - I2C BUS INTERFACE BUS INTERFACE (Cont’d) INTERRUPT MASK REGISTER (I2CIMR) R255 - Read / Write Register Page: 20 Reset Value: 00xx 0000 (x0h) 7 RXD TXD REOBP TEOBP Bit 7 = RXDM ...
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I C BUS INTERFACE (Cont’d) 2 Table 38 BUS Register Map and Reset Values Address Register 7 Name (Hex.) I2CCR - F0h Reset Value 0 I2CSR1 EVF F1h Reset Value 0 I2CSR2 - F2h Reset Value 0 ...
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ST92163R4 - A/D CONVERTER (A/D) 8.6 A/D CONVERTER (A/D) 8.6.1 Introduction The 8 bit Analog to Digital Converter uses a fully differential analog configuration for the best noise immunity and precision performance. The analog voltage references of the converter are ...