EVAL-ADT7462EBZ ON Semiconductor, EVAL-ADT7462EBZ Datasheet - Page 72

• Manufacturer Part Number: EVAL-ADT7462EBZ
• Description: BOARD EVALUATION FOR ADT7462
• Manufacturer: ON Semiconductor
• Type: Temperature Sensorr

Specifications of EVAL-ADT7462EBZ

• Contents: Evaluation Board
• For Use With/related Products: ADT7462
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. POR = 0x38, Lock = N, SW Reset = Y.
1. POR = 0x00, Lock = N, SW Reset = Y.
1. POR = 0x00, Lock = N, SW Reset = Y.
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 68. Register 0x35 — Digital Mask Register
Table 69. Register 0x36 — GPIO Mask Register
Table 70. Register 0x37 — EDO 1 Mask Register
Table 71. Register 0x38 — EDO 2 Mask Register
[2:0]
Bit
Bit
Bit
Bit
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
VID Comparison
Chassis Intrusion
FAN2MAX
Reserved
Reserved
Reserved
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO1
GPIO2
GPIO3
GPIO4
GPIO1
GPIO2
GPIO3
GPIO4
SCSI1
SCSI2
Name
Name
Name
Name
Temp
Temp
Fan
Fan
Volt
Volt
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reserved for future use.
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
A 1 masks ALERTs for the corresponding interrupt status bit.
A 1 masks ALERTs for the corresponding interrupt status bit.
A 1 masks ALERTs for the corresponding interrupt status bit.
A 1 masks ALERTs for the corresponding interrupt status bit.
A 1 masks ALERTs for the corresponding interrupt status bit.
A 1 masks ALERTs for the corresponding interrupt status bit.
A 1 masks ALERTs for the corresponding interrupt status bit.
A 1 masks ALERTs for the corresponding interrupt status bit.
A 1 masks GPIO1 from causing an EDO1 assertion.
A 1 masks GPIO2 from causing an EDO1 assertion.
A 1 masks GPIO3 from causing an EDO1 assertion.
A 1 masks GPIO4 from causing an EDO1 assertion.
Unused.
A 1 masks a fan−fail condition from causing an EDO1 assertion.
A 1 masks a THERM condition from causing an EDO1 assertion.
A 1 masks a voltage exceed limit condition from causing an EDO1 assertion.
A 1 masks GPIO1 from causing an EDO2 assertion.
A 1 masks GPIO2 from causing an EDO2 assertion.
A 1 masks GPIO3 from causing an EDO2 assertion.
A 1 masks GPIO4 from causing an EDO2 assertion.
Unused.
A 1 masks a fan−fail condition from causing an EDO2 assertion.
A 1 masks a THERM condition from causing an EDO2 assertion.
A 1 masks a voltage exceed limit condition from causing an EDO2 assertion.
(Note 1)
http://onsemi.com
(Note 1)
(Note 1)
(Note 1)
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Description
Description
Description
Description