DK-SI-2SGX90N Altera, DK-SI-2SGX90N Datasheet - Page 36

• Manufacturer Part Number: DK-SI-2SGX90N
• Description: SI KIT W/SII GX EP2SGX90N
• Manufacturer: Altera
• Series: Stratix® IIr
• Type: DSPr

Specifications of DK-SI-2SGX90N

• Contents: Dev Board, Quartus®II Web Edition, Cables, Accessories, Reference Designs and Demos
• For Use With/related Products: Stratix ll GX 2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1724

Design Walkthrough With Troubleshooting and Debugging Solutions
A–8
Transceiver Signal Integrity Development Kit, Stratix II GX Edition
Troubleshooting Solutions
This section provides troubleshooting solutions. If your transaction is not
successful, review the following troubleshooting suggestions:
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Debugging Using the SignalTap
In the kit’s Examples\SII_GX_SI_NonGUI_Design directory there is a
Quartus
design1.stp file is part of the .qar file and contains a variety of debugging
signals. The available signals are:
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If the LED D1 is not illuminated, the system may not be receiving the
clock cycles. Ensure that the slide switch (S9) is in the oscillator
position (OSC). Also, ensure that switch 6 of the clock setting DIP
switch bank (S8) is set to OPEN.
If the LED D2 is not illuminated, the receiver cannot sync to the
transmitted data. To remedy this problem:
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If the LED D3 is not ON, the data checker did not receive the
expected data. To remedy this problem:
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If the display shows EE, the DIP switch selection for PMA_controls
is not correct.
All resets going into the transceivers
Status signals from transceivers: rx_freqlocked,
rx_syncstatus
Input push button and DIP switch values
Reconfiguration block signals
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Data generator and checker signals
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Ensure that serial loopback is ON if external loopback is not
completed.
If external loopback is completed, check the quality of the cables
used.
Assert the system_reset push button switch.
Ensure that the data pattern of the DIP switch is set to PRBS7 or
PRBS23.
High frequency data patterns do not have a data checker.
Therefore, the LED D3 will be off when high frequency patterns
are used.
Inputs and outputs of VOD, preemphasis, equalization and DC
gain values
Read, write, busy, and data valid signals
Parallel data output to the transceiver
Getting Started User Guide
II archive (.qar) file containing the example design project. The
®
II Embedded Logic Analyzer
Altera Corporation
June 2006