DK-SI-2SGX90N Altera, DK-SI-2SGX90N Datasheet - Page 29

SI KIT W/SII GX EP2SGX90N

DK-SI-2SGX90N

Manufacturer Part Number
DK-SI-2SGX90N
Description
SI KIT W/SII GX EP2SGX90N
Manufacturer
Altera
Series
Stratix® IIr
Type
DSPr
Datasheet

Specifications of DK-SI-2SGX90N

Contents
Dev Board, Quartus®II Web Edition, Cables, Accessories, Reference Designs and Demos
For Use With/related Products
Stratix ll GX 2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1724

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-SI-2SGX90N
Manufacturer:
ALTERA
0
Design Features
Altera Corporation
June 2006
This manually-controlled (non-GUI based) example is a one channel
design using the microstrip transceiver quad at 6.25 Gbps. The input
clock frequency is 156.25 MHz and the interface is 40 bits wide. The
TX_P0 is connected to A4 and RX_P0 to C1. The other transceiver quads
that are not used are powered off. Data patterns supported are PRBS23,
PRBS7, and the high frequency pattern (1010).
1
The following parameters can be controlled during run-time:
The parameters are controlled using a combination of DIP switches and
push-button switches. See
for the design is 156.25 MHz. Please set switch 6 in the clock setting DIP
switch bank (S8) to OPEN.
position.
Figure A–1. Clock Setting DIP Switch Bank (All Switches In Closed Position)
Preemphasis—Main tap (The other tap controls are not available.)
Equalization
DC gain
VOD
Data pattern select
Serial loopback
The checkers are only available for the PRBS23 and PRBS7 data
patterns.
Getting Started User Guide
Transceiver Signal Integrity Development Kit, Stratix II GX Edition
Appendix A. Non-GUI Based
Figure A–1
Table
A–1. The on-board frequency rate used
shows all the switches in the closed
Example Design
A–1

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