DK-SI-2SGX90N Altera, DK-SI-2SGX90N Datasheet - Page 18

• Manufacturer Part Number: DK-SI-2SGX90N
• Description: SI KIT W/SII GX EP2SGX90N
• Manufacturer: Altera
• Series: Stratix® IIr
• Type: DSPr

Specifications of DK-SI-2SGX90N

• Contents: Dev Board, Quartus®II Web Edition, Cables, Accessories, Reference Designs and Demos
• For Use With/related Products: Stratix ll GX 2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1724

Test the Transceiver Performance Using Pre-Defined Designs
Test the
Transceiver
Performance
Using
Pre-Defined
Designs
2–10
Transceiver Signal Integrity Development Kit, Stratix II GX Edition
Note to
(1)
gxbguictrl_top1.sof 6.25
gxbguictrl_top2.sof 5
Table 2–3. Transceiver Test Design Results
The clock input can also be given from an external source. The frequency of the clock should be selected such that
the data rate in Quads 1 and 3 should be within the 6.375 Gbps - 3.126 Gbps range. For Quad2 the data rate should
be within the 3.125 Gbps-622 Mbps range. See
File Name
Table
2–3:
f
Quad 1 Channel 1
Data Rate (Gbps)
The kit provides pre-defined test designs and an easy-to-use demo
application with a custom graphical user interface (GUI). The demo
application’s GUI allows extensive transceiver channel testing at various
data rates and clocking schemes.
This section provides:
■
■
Pre-Defined Test Designs
Altera engineers created a set of pre-defined test designs for you to
evaluate Stratix II GX device transceiver performance and board features.
As you can tell from the data listed in
dramatically when choosing from various clocking schemes and data
rates.
Table 2–3
Refer to the section
page 2–8
the Stratix II GX device with one of the pre-defined designs. The
CONF DONE LED (D14) illuminates upon successful device
configuration. Also, the 7-segment display shows the programmed
SOF/POF number. For example, for the gxbguictrl_top1.sof the
7-segment display indicates the SOF with 01, and with the
gxbguictrl_top2.sof the 7-segment display indicates the SOF with 02.
Pre-defined test design results
Demo application GUI tutorial
for information on using the JTAG interface when configuring
Getting Started User Guide
lists the default transceiver settings.
3.125
2.5
Quad 2 Channel 1
Data Rate (Gbps)
Table
“Connect the Cables to the Board and Computer” on
2–4.
6.25
5
Quad 3 Channel 1
Data Rate (Gbps)
Table
2–3, the results can vary
Clock from
156.25-MHz
oscillator
Clock from
156.25-MHz
oscillator
Altera Corporation
Clocking Scheme
Note (1)
June 2006