HIP4082EVAL Intersil, HIP4082EVAL Datasheet - Page 2

• Manufacturer Part Number: HIP4082EVAL
• Description: EVAL BOARD FET DRIVER HIP4082
• Manufacturer: Intersil
• Type: FET Driverr

Specifications of HIP4082EVAL

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: HIP4082
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

second inverter converts the 160V
square-wave representation of a sin-wave having a
frequency of 55Hz with a peak voltage matching the high
voltage DC bus potential. A simple feed forward technique
regulates the AC secondary voltage to 115V
battery varies over a range of approximately 11V to 15V.
(Through component modification, 230VAC is possible.)
The aforementioned features are similar to those of at least
one commercially available battery inverter (Radio Shack,
Catalog number 22-132A). Thermal limiting on the
evaluation unit is approximately 120W at ambient
temperatures to 30
in order to allow the unit to be operated without a heat-
sinking enclosure. This allows users to probe various points
in order to provide a better understanding of circuit
operation.
Primary Inverter Design
Input Filter
The primary-side inverter is comprised of a simple R-C input
filter. Capacitors, C
for the inverter bridge comprised of Q
in the schematic (see Appendix). To aid this process,
Resistor, R
parallel C
with voltage transients across the battery terminals. To
prevent these transients from exceeding the V
ratings of the HIP4082 and other ICs on the primary inverter
section, R
less.
Primary Inverter Waveform Generation
To minimize the size of the secondary filter, a 50% duty cycle
square-wave was chosen for primary excitation. With a
nearly constant, low-ripple voltage, secondary filtering can
be minimized and ripple nearly eliminated. An inexpensive
Intersil ICM7555 timer was chosen. This timer, an improved
555 timer, reduces V
spikes, thereby minimizing bias current requirements.
The timer, U
by tying pins 2 and 6 of the timer together. The astable mode
requires only one resistor, R
duty-cycle square-wave is available at the “OUT” (pin 3)
terminal of timer, U
The timer ‘out’ pin drives the clock input, pin 3, of a CA4013
D-flip-flop connected as a divide by two circuit. To
accomplish the divide-by-two function, the QNOT output of
the flip-flop is fed back to its own data, D, input. The Q and
QNOT outputs of the CA4013 provide an exact 50% duty-
cycle square-wave at half the timer’s output frequency and
are applied to the ALI-BHI and the AHI-BLI gate control
inputs of the HIP4082 respectively as shown in Figure 2. The
ICM7555 clock frequency was chosen to be 120kHz so that
the primary inverter frequency would be 60kHz.
5
7
37
and C
, C
1
, operates in the astable mode, accomplished
and ceramic, non-inductive capacitor, C
4
and D
6
. Automotive applications can be fraught
o
5
1
C (a little lower than the competitive unit)
, as shown in Figure 1.
and C
CC
3
clamp the V
to ground cross conduction current
6
1
provide a stiff, sag-free source
, and one capacitor, C
2
DC
CC
1
voltage into a quasi-
through Q
voltage to 16V or
AC
CC
while the
4
Application Note 9611
voltage
as shown
3
. A 50%
7
,
Choosing Proper Dead-Time
The dead-time chosen for eliminating shoot-through currents
in the Q
value of R
HIP4082. The 15K value chosen provides approximately
0.5s of dead-time, sufficient to avoid shoot-through when
using RFP70N06 MOSFETs. Refer to the HIP4082 data
sheet, File Number 3676, Figure 16 for dead-time versus
delay resistance characteristics.
Controlling di/dt and Switching Losses
Choice of gate resistor values for R
upon several factors. The gate resistors tailor the turn-on and
turn-off rise times of the power MOSFETs and the
commutating di/dt. The di/dt affects commutation losses and
body diode recovery losses. As di/dt increases, recovery
losses increase, but the commutation losses decrease. As
di/dt decreases, recovery losses decrease, and commutation
losses increase. Generally there is an ideal commutation di/dt
which minimizes the sum of these switching losses.
1
2
1
2
CH1 = 5V
CH1 = 10V
FIGURE 2. INPUT WAVEFORMS TO THE HIP4082
1
-Q
2
4
connected between the DEL and V
FIGURE 1. 555 TIMER WAVEFORMS
and Q
CH2 = 5V
CH2 = 10V
2
-Q
3
MOSFET pairs is determined by the
M = 2.5µs CH1
M = 2.5µs CH1
3
-R
5
, and R
8
SS
4.2V
4.2V
is based
pins of the
C2 (MAX)
9V
C1 FREQ.
118.28kHz
C2 (MAX)
13.8V
C1 FREQ.
59.544kHz
LOW
SIGNAL
AMPL.