SI5318-EVB Silicon Laboratories Inc, SI5318-EVB Datasheet - Page 23

• Manufacturer Part Number: SI5318-EVB
• Description: BOARD EVALUATION FOR SI5318
• Manufacturer: Silicon Laboratories Inc
• Type: Precision Clockr

Specifications of SI5318-EVB

• Contents: Fully Assembled Evaluation Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SI5318
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1179

*Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
Pin #
G1
H1
D8
H3
F1
F8
logic low state if the input is not driven from an external source.
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
RSTN/CAL
DH_ACTV
Pin Name
LOS
Table 10. Si5318 Pin Descriptions (Continued)
I/O
O
O
I*
I*
Signal Level
LVTTL
LVTTL
LVTTL
LVTTL
Rev. 1.0
Input Frequency Range Select.
Pins(INFRQSEL[2:0]) select the frequency range for
the input clock, CLKIN. (See Table 3 on page 7.)
000 = Reserved.
001 = 19 MHz range.
010 = 39 MHz range.
011 = 78 MHz range.
100 = 155 MHz range.
101 = Reserved.
110 = Reserved.
111 = Reserved.
Loss-of-Signal (LOS) Alarm for CLKIN.
Active high output indicates that the Si5318 has
detected missing pulses on the input clock signal.
The LOS alarm is cleared after either 100 ms or
13 seconds of a valid CLKIN clock input, depending
on the setting of the VALTIME input.
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the current
state of the DSPLL and forces the DSPLL to continue
generation of the output clock with no additional
phase or frequency information from the input clock.
Reset/Calibrate.
When low, the internal circuitry enters the reset mode
and all LVTTL outputs are forced into a high-imped-
ance state. Also, the CLKOUT+ and CLKOUT– pins
are forced to a nominal CML logic LOW and HIGH
respectively. This feature is useful for in-circuit test
applications.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition, enables the device
outputs, and initiates self-calibration of the DSPLL.
Upon completion of self-calibration, the DSPLL
begins to lock to the selected clock input signal.
Description
Si5318
23