HS7760KCI02H Renesas Electronics America, HS7760KCI02H Datasheet - Page 265

• Manufacturer Part Number: HS7760KCI02H
• Description: ON CHIP DEBUG EMULATOR W/TRACE
• Manufacturer: Renesas Electronics America

Specifications of HS7760KCI02H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The events can be counted even if the conditions shown in table 7.5 are generated, in addition to
the normal count conditions.
Table 7.5 Performance Count Conditions
Event
Instruction cache miss
count
TLB miss count
Instruction fetch count
Instruction issue count
FPU instruction issue
count
UBC satisfaction count
Pipeline freeze due to
cache miss
Count Condition
When the TLB miss is canceled by an exception
having a higher priority than that of the TLB miss
When the instruction fetch request by the CPU is
accepted.
Counts two when two instructions are issued at the
same time.
Counts one to three when instruction fetch
exception (instruction address error, instruction
TLB miss exception, or instruction TLB protection
violation exception) occurs.
LDS Rm, FPUL, LDS.L @Rm+, FPUL,
LDS Rm, FPSCR, LDS.L @Rm+, FPSCR,
STS FPUL, Rn, STS.L FPUL, @-Rn,
STS FPSCR, Rn, STS.L FPSCR, @-Rn
Others: instructions that the instruction code is
H'Fxxx
Also counts when the emulator uses the UBC as
Break Condition 6,7.
Includes the following freeze times:
Includes instruction fetch for the cache-off area
to count the number of times the instruction has
not been fetched in one cycle.
When a cache miss occurs during an overrun
fetch generated at exception.
Counts two when two instructions are issued at
the same time.
The following shows the FPU instructions:
At internal RAM or internal I/O space access
At instruction or operand access without cache
Target Mode
EC
DT and ET
EF and EA
E
E and E2
EFP
UA and UB
PFCF and PFCD
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