HS7760KCI02H Renesas Electronics America, HS7760KCI02H Datasheet - Page 230

• Manufacturer Part Number: HS7760KCI02H
• Description: ON CHIP DEBUG EMULATOR W/TRACE
• Manufacturer: Renesas Electronics America

Specifications of HS7760KCI02H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11. An address (physical address) to which a BREAKPOINT is set is determined when the
12. When a BREAKPOINT is set to the cacheable area, the cache block containing the
13. While a BREAKPOINT is set, the contents of the instruction cache are disabled at execution
6.5.4
The JTAG clock (TCK) and AUD clock (AUDCK), which can be set in the [Configuration] dialog
box, have notes as follows.
Set the JTAG clock (TCK) frequency to less than the frequency of the SH7760 peripheral module
clock (CKP).
The AUD clock (AUDCK) frequency operates up to 50 MHz. Do not set the frequency to more
than 50 MHz.
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If a program is executed again without clearing the BREAKPOINT set at the address in which
the TLB error occurs, a TLB error will occur again. Accordingly, clear the BREAKPOINT
before execution.
BREAKPOINT is set. Accordingly, even if the VP_MAP table is modified after
BREAKPOINT setting, the BREAKPOINT address remains unchanged. When a
BREAKPOINT is satisfied with the modified address in the VP_MAP table, the cause of
termination displayed in the status bar and the [System Status] window is ILLEGAL
INSTRUCTION, not BREAKPOINT.
BREAKPOINT address is filled immediately before and after user program execution.
completion.
Notes on Using the JTAG Clock (TCK) and AUD Clock (AUDCK)
Figure 6.11 Message Box for Clearing a TLB Error