HS7760KCI02H Renesas Electronics America, HS7760KCI02H Datasheet - Page 222

• Manufacturer Part Number: HS7760KCI02H
• Description: ON CHIP DEBUG EMULATOR W/TRACE
• Manufacturer: Renesas Electronics America

Specifications of HS7760KCI02H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3. Low-Power Modes (Sleep, Standby, and Module Standby)
Notes: 1. After the sleep mode is cleared by a break, execution restarts at the instruction
4. RESET Signals (/RESET and /MRESET)
Note: Do not break the user program when the /RESET, /MRESET, /BREQ, and /RDY
5. Direct Memory Access Controller (DMAC)
6. Internal I/O Registers
Note: As default, SDMR2 and SDMR3 are specified in the I/O-register definition file as the
7. Memory Access during Emulation
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For low-power consumption, the SH7760 has sleep, standby, and module standby modes.
The sleep and standby modes are switched using the SLEEP instruction. When the emulator is
used, the sleep and standby modes can be cleared by either normal clearing or with the [Stop]
button. Note that, however, if a command has been entered in standby mode or module
standby mode, the TIMEOUT error is displayed.
The SH7760 RESET signals (/RESET and /MRESET) are only valid during emulation started
with clicking the GO or STEP-type button. If these signals are input from the user system in
command input wait state, they are not sent to the SH7760.
The DMAC operates even in the command wait state. When a data transfer request is
generated, the DMAC executes DMA transfer.
In the emulator, the internal I/O registers can be accessed from the [I/O Registers] window.
However, pay attention when accessing the SDMR register of the bus-state controller. Before
accessing the SDMR register, specify addresses to be accessed in the I/O-register definition
file (SH7760.IO) and then activate the HDI. For details on I/O-register definition files, refer to
the Hitachi Debugging Interface User's Manual.
When a memory is accessed from the memory window, etc. during user program execution,
the user program is resumed after it has stopped in the E10A emulator to access the memory.
Therefore, realtime emulation cannot be performed.
2.
3.
4.
signals are being low. A TIMEOUT error will occur. If the /BREQ and /RDY
signals are fixed to low during break, a TIMEOUT error will occur at memory
access.
area-2 SDMR register and area-3 SDMR register, respectively.
following the SLEEP instruction.
If the memory is accessed or modified in sleep mode, the sleep mode is cleared
and execution starts at the instruction following the SLEEP instruction.
If the state transits to the hardware standby mode, a TIMEOUT error occurs.
When the SLEEP instruction is executed by STEP-type commands, set [Rate] to
6 to use [Step…] from the [Run] menu. If [Rate] is 5 or less, a Communication
timeout error occurs.