HS7750KCI01H Renesas Electronics America, HS7750KCI01H Datasheet - Page 30
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HS7750KCI01H
Manufacturer Part Number
HS7750KCI01H
Description
ON CHIP DEBUG EMULATOR
Manufacturer
Renesas Electronics America
Specifications of HS7750KCI01H
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 2.8 Measurement Items (cont)
Event
Two-instruction concurrent
execution count
FPU instruction execution
count
TRAPA instruction
execution count
Interrupt count (normal)
Interrupt count (NMI)
Instruction cache-fill cycle ECF
Operand cache-fill cycle
Elapsed-time cycle
Note: For the non-cache operand accesses due to the PREF instruction or TLB.c=0, the correct
The events can be counted even in the conditions shown in table 2.9, in addition to the normal
count conditions.
22
value cannot be counted.
Keyword Description
E2
EFP
ETR
INT
NMI
OCF
TM
The number of times two instructions are issued at the
same time.
The number of times FPU instruction is issued.
The number of times the TRAPA instruction is executed.
The number of interrupts (generally except for NMI).
The number of NMI interrupts.
The number of instruction cache-fill cycles.
The number of operand cache-fill cycles.
The number of cycles for elapsed time.