HS7750KCI01H Renesas Electronics America, HS7750KCI01H Datasheet - Page 24

• Manufacturer Part Number: HS7750KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750KCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.2.4
Set the JTAG clock (TCK) frequency to lower than the frequency of the SH7750 or SH7750S
peripheral module clock (CKP).
2.2.5
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions. Accordingly, it can be set only
3. During step operation, a BREAKPOINT is disabled.
4. Conditions set at Break Condition 3 are disabled when an instruction to which a
5. When execution resumes from the address where a BREAKPOINT is specified, single-step
6. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
7. When the [Normal] option is selected in the [Memory area] group box in the [General] page of
16
(6) Do not use the continuous trace for a program in which an SGR value is referred to with
(7) When continuous trace is used, do not enable user interrupt by the INTERRUPT command
to the internal RAM area. However, a BREAKPOINT cannot be set to the following
addresses:
In addition, do not perform memory write, BREAKPOINT, or download even if the memory
space can only be written by the MMU.
BREAKPOINT has been set is executed. Do not set a BREAKPOINT to an instruction in
which Break Condition 3 is satisfied.
operation is performed at the address before execution resumes. Therefore, realtime operation
cannot be performed.
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
the [Configuration] dialog box, a BREAKPOINT is set to a physical address or a virtual
address according to the SH7750 or SH7750S MMU state during command input when the
VPMAP_SET command setting is disabled. The ASID value of the SH7750 or SH7750S
PTEH register during command input is used. When VPMAP_SET command setting is
An address whose memory content is H'003B
An area other than the CS0 to CS6 areas and the internal RAM area
An instruction in which Break Condition 4 is satisfied
A slot instruction of a delayed branch instruction
the interrupt handler. In the SH7750 E10A emulator, the contents of the SGR register are
lost when the user program breaks. Since the user program execution stops at constant
intervals while the continuous trace is selected, the contents of the SGR register will be
lost.
during the emulator command wait state or user program execution.
Notes on Using the JTAG Clock (TCK) and AUD Clock (AUDCK)
Notes on Setting the [Breakpoint] Dialog Box