DSP56F803EVM Freescale Semiconductor, DSP56F803EVM Datasheet - Page 20

KIT EVALUATION FOR DSP56F803

DSP56F803EVM

Manufacturer Part Number
DSP56F803EVM
Description
KIT EVALUATION FOR DSP56F803
Manufacturer
Freescale Semiconductor

Specifications of DSP56F803EVM

Processor To Be Evaluated
56F803
Data Bus Width
16 bit
Interface Type
RS-232, JTAG
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
2.2 Program and Data Memory
The 56F803EVM uses one bank of 128K 16-bit Fast Static RAM (GSI GS72116, labeled U2)
for external memory expansion; see the FSRAM schematic diagram in
memory bank is split into two logical memory banks of 64Kx16-bits: one for Program memory
and the other for Data memory. By using the device’s program strobe, PS, signal line along with
the memory chip’s A0 signal line, half of the memory chip is selected when Program memory
accesses are requested and the other half of the memory chip is selected when Data memory
accesses are requested. This memory bank will operate with zero wait-state accesses while the
56F803 is running at 70MHz. However, when running at 80MHz, the memory bank operates
with four wait-state accesses. This memory bank can be disabled by removing the jumper at JG5.
2-4
Figure 2-1. Schematic Diagram of the External Memory Interface
Connect Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
DSP56F803EVM User Manual, Rev. 5
56F803
D0-D15
A0-A15
WR
RD
PS
JG5
+3.3V
A1-A16
D0-D15
RD
CS
WR
A0
GS72116
Figure
Freescale Semiconductor
2-1. This physical

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