COP8-PGMA-DS44P National Semiconductor, COP8-PGMA-DS44P Datasheet - Page 21

• Manufacturer Part Number: COP8-PGMA-DS44P
• Description: PGMR ADAPTER/COP8 DIP,SOIC,PLCC
• Manufacturer: National Semiconductor

Specifications of COP8-PGMA-DS44P

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *COP8-PGMA-DS44P

Instruction Execution Time
Most instructions are single byte (with immediate addressing
mode instruction taking two bytes).
Most single instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
Arithmetic and Logic Instructions
Memory Transfer Instructions
Note 24: =
Instructions Using A & C
Transfer of Control Instructions
JMPL
>
Memory location addressed by B or X or directly.
X A, (Note 24)
LD A, (Note 24)
LD B,Imm
LD B,Imm
LD Mem,Imm
LD Reg,Imm
3/4
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
CLRA
INCA
DECA
LAID
DCORA
RRCA
SWAPA
SC
RC
IFC
IFNC
Register
[B] [X]
1/1 1/3
1/1 1/3
Indirect
2/2
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
2/3
2/3
3/3
Immed.
21
2/2
1/1
2/3
2/3
See the BYTES and CYCLES per INSTRUCTION table for
details.
BYTES and CYCLES per
INSTRUCTION
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
The following table shows the instructions assigned to un-
used opcodes. This table is for information only. The opera-
tions performed are subject to change without notice. Do not
use these opcodes.
Direct
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
1/3
3/4
3/4
3/4
[B+, B−]
Auto Incr & Decr
Register Indirect
1/2
1/2
2/2
[X+, X−]
Immed.
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
1/3
1/3
(If B
(If B
>
<
15)
16)
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