COP8-PGMA-DS44P National Semiconductor, COP8-PGMA-DS44P Datasheet - Page 17

• Manufacturer Part Number: COP8-PGMA-DS44P
• Description: PGMR ADAPTER/COP8 DIP,SOIC,PLCC
• Manufacturer: National Semiconductor

Specifications of COP8-PGMA-DS44P

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *COP8-PGMA-DS44P

Functional Description
time into the timer, which continues to run. By alternately
loading in the on time and the off time at each successive
interrupt a PWM frequency can be easily generated.
Control Registers
CNTRL REGISTER (ADDRESS X’00EE)
The Timer and MICROWIRE/PLUS control register contains
the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by
IEDG
MSEL
TRUN
TC3
TC2
TC1
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits:
GIE
ENI
BUSY MICROWIRE/PLUS busy shifting
IPND
ENTI
TPND Timer interrupt pending
C
HC
Addressing Modes
REGISTER INDIRECT
This is the “normal” mode of addressing. The operand is the
memory addressed by the B register or X register.
TC1
BIT
HC
BIT
7
7
C
TC2
Global interrupt enable
External interrupt enable
External interrupt pending
Timer interrupt enable
Carry Flag
Half carry Flag
TPND
External interrupt edge polarity select
(0 = rising edge, 1 = falling edge)
Enable MICROWIRE/PLUS functions SO and
SK
Start/Stop the Timer/Counter (1 = run, 0 = stop)
Timer input edge polarity select (0 = rising
edge, 1 = falling edge)
Selects the capture mode
Selects the timer mode
FIGURE 11. Timer Application
TC3
ENTI
TRUN
IPND
MSEL
BUSY
IEDG
(Continued)
DS010802-13
ENI
SL1
GIE
SL0
BIT
BIT
0
0
17
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the
operand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically increments
or decrements the B or X register after executing the instruc-
tion.
RELATIVE
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from −31 to +32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruc-
tion). There are no “pages” when using JP, all 15 bits of PC
are used.
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
E0 to EF
00 to 6F
70 to 7F
80 to BF
F0 to FF
DD–DF
E0–E7
C0 to
D0 to
CF
DF
DA
DB
DC
EA
EB
EC
ED
EE
FC
FD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
E8
E9
EF
On Chip RAM Bytes
Unused RAM Address Space (Reads as all Ones)
Expansion Space for future use
Expansion Space for I/O and Registers
On Chip I/O and Registers
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D
On Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE/PLUS Shift Register
Timer Lower Byte
Timer Upper Byte
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register
On Chip RAM Mapped as Registers
X Register
SP Register
Contents
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