IRMD22381Q International Rectifier, IRMD22381Q Datasheet
IRMD22381Q
Specifications of IRMD22381Q
Related parts for IRMD22381Q
IRMD22381Q Summary of contents
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Features • Floating channel up to +600V or • “soft” over-current shutdown turns off desaturated output • Integrated desaturation circuit • Active biasing on sensing desaturation input • Two stage turn on output for di/dt control • Integrated brake IGBT ...
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Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to V resistance and power dissipation ratings are measured under board mounted and still air conditions. ...
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Static Electrical Characteristics 15V and T BIAS CC, BS1,2,3 A I/O diagrams don’t show ESD protection circuits. Pin Symbol Definition V V supply undervoltage ...
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Pin: FAULT/N, VFH, VFL V is referenced to V OLVF ss Symbol V VFH or VFL low level output voltage OLVF VFH or VFL output on resistance R ON,VF FAULT/N low on resistance R ON,FLT Pin: DSL, DSH, DSB V ...
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Pin: HOP, LOP, HOQ, LOQ The V and I parameters are referenced to COM and and LO . 1,2,3 1,2,3 Symbol Definition V High level output voltage switching). HOP=HOQ, LOP=LOQ. I Output high first ...
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Pin: BR The V and I parameters are referenced to COM and are applicable to BR output . O O Symbol Definition V BR high level output voltage, V OHB V BR low level output voltage, V OLB I BR ...
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AC Electrical Characteristics cont 15V BIAS CC BS S1, Symbol Propagation Delay Characteristics cont. t Soft shutdown minimum pulse width of desat DS t Soft shutdown duration period SS t ...
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Figure 7: Switching Time Waveforms Figure 8: Low Side Desat Soft Shutdown Timing Waveform 8 ...
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Figure 9: High Side Desat Soft Shutdown Timing Waveform Figure 10: Brake Desat Timing Waveform 9 ...
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Figure 11: Desat Timing Diagram 10 ...
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HIN LIN DTL off HO (HOP=HOQ=HON) 50% 10% DT 90% 50% LO (LOP=LOQ=LON) V B1,2,3 V DESAT- DSH 1,2,3 V S1,2,3 V B1,2,3 DSL V 1,2,3 V S1,2,3 t VFHL1,2 90% VFH 1,2 VFLH1,2,3 V ...
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Figure 14: Shutdown Timing Figure 15: Fault Duration with Pending Faultclear Waveform (See paragraph 1.4.5 on page 21) Figure 16: Output source current 12 ...
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Lead Assignments Lead Definitions Symbol V Low side supply voltage CC V Logic Ground SS HIN /N Logic inputs for high side gate driver outputs (HOP 1,2,3 LIN Logic input for low side gate driver outputs (LOP 1,2,3 FAULT/N Fault ...
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Lead Definitions continued Symbol BR Brake driver output COM Brake and Low side drivers return VB High side gate driver floating supply 1,2,3 HOP High side driver sourcing output 1,2,3 HOQ High side driver boost sourcing output 1,2,3 HON High ...
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Functional block diagram SCHMITT HIN1 T RIGGER 100nsec INPUT & minimum SHOOT Deadtime THROUGH LIN1 PREVENTION VFH1 SCHMITT HIN2 T RIGGER 100nsec INPUT & minimum SHOOT Deadtime THROUGH LIN2 PREVENTION VFH2 SCHMITT HIN3 T RIGGER 100nsec INPUT & minimum SHOOT ...
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State diagram Stable States − FAULT − Normal operation − UNDERVOLTAGE V CC − SHUTDOWN (SD) − UNDERVOLTAGE V BS NOTE 1: a change of logic value of the signal labeled on lines (system variable) generates a state transition. NOTE ...
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Logic Table Output drivers status description HO/LO/BR HOP/LOP HOQ/LOQ status 0 HiZ HiZ (after t SSD HiZ HiZ LO/HO/BR Output follows inputs INPUTS Operation HIN/N LIN Normal Operation 1 0 Anti Shoot 0 ...
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Timing and logic state diagrams description The following picture (Figure 18) shows the input/output logic diagram. Referred to timing diagram of Figure 18: A. When the input signals are on together the outputs go off (anti-shoot through). B. The HO ...
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FEATURES DESCRIPTION 1.1 Start-up sequence Device starts in FAULT condition at power-up unless FAULT clear condition is forced (i.e. LIN1=LIN2=LIN3=0 for at least t case FAULT is asserted for t , then resets). fltclr In FAULT condition driver outputs ...
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Figure 19: high and low side output stage for channels ____ HIN1 Schmitt trigger input 100ns & minimum shoot through deadtime prevention LIN1 Clear LIN2 logic LIN3 _____ FAULT R Fault S Q duration (t VSS fault ...
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The external sensing diode should have BV>600V (or 1200V depending on application) and low stray capacitance (in order to minimize noise coupling and switching delays). The diode is biased by a dedicated circuit for IGBT driver outputs (see the active-bias ...
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DSH/L pin decreases. At this point the deactivates, in order to reduce the bias current of the diode as shown in Figure 21. Figure ...
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Sizing tips 2.1 Bootstrap supply The V voltage provides the supply to the high BS1,2,3 side drivers circuitry of the IR22381/IR21381. V supply sit on top of the V voltage and so it must be S floating. The bootstrap ...
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And the bootstrap capacitor must be: 133 nC ≥ BOOT NOTICE: Here above V has been chosen 18V as an example. IGBTs can ...
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I C RES dV/ 90% C RES 10% 10 Don R Figure 24: Nomenclature 2.2.1 Sizing the ...
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Sizing the turn-off gate resistor The worst case in sizing the turn-off resistor R when the collector of the IGBT in off state is forced to commutate by external events (i.e. the turn-on of the companion IGBT). In this case ...
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Table 3: RGoff sizing IGBT Vth(min) CRESoff GB15XP120K* 5 38pF GB05XP120K 5 12pF IRG4PH20K(D) 5 11pF * sized with 18V supply 3 PCB LAYOUT TIPS 3.1 Distance from voltage The IR22381/IR21381Q pin out lacks some pins (see ...
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TOP(Gate Drive) b) BOTTOM (GND) 28 ...
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MID (VCC/COM/DCP) Figure 28: layout example: top (a), internal layer (b) and bottom (c) layer 29 ...
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Case Outline Qualification Level: Industrial level, MSL3, Lead-free. ESD Classification: Human Body Model (HBM): Class 2, per JESD22-A114-B Machine Model (MM): Class B, per EIA/JESD22-A115-A WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 IR22381QPBF/IR21381Q(PbF) This product ...