RLINK-ST STMicroelectronics, RLINK-ST Datasheet - Page 25

• Manufacturer Part Number: RLINK-ST
• Description: ADAPTER USB-JTAG FOR DK3300
• Manufacturer: STMicroelectronics

Specifications of RLINK-ST

• Accessory Type: Cable - ISP (In-System Programming)
• For Use With/related Products: ST Micro - DK3300, DK3400
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4831

STR71xF
Table 7.
20 G2
21 G3 RTCXTI
22 H4 RTCXTO
23 F3 STDBY
24 G4 RSTIN
25 H5 V
26 F4 V
27 G5 V
28 H6 V
29 E4 V
30 G6 V
31 F5
32 H7
33 H8
34 G8
35 F8
Pin n°
P0.15/
WAKEUP
P1.0/T3.OCM
PB/AIN.0
P1.1/T3.ICAP
A/T3.EXTCLK
/AIN.1
P1.2/T3.OCM
PA/AIN.2
P1.3/T3.ICAP
B/AIN.3
P1.4/T1.ICAP
A/T1.EXTCLK
SSBKP
18BKP
18
SS18
DDA
SSA
Pin name
STR711/STR712/STR715 pin description
I/O
I/O pu
I/O pu
I/O pu
I/O pu
I/O pu
S
S
S
S
I
I
C
C
C
C
C
C
C
T
Input
S
S
T
T
T
T
T
T
T
T
X
4mA
4mA
4mA
4mA
4mA
4mA
Output
X
X
X
X
X
X
X
X
X
X
X
X
X
X Reset input
X Stabilization for low power voltage regulator.
X
Port 0.15 Wakeup from Standby mode input.
Note: This port is input only.
Realtime Clock input and input of 32 kHz oscillator
amplifier circuit
Output of 32 kHz oscillator amplifier circuit
Input: Hardware Standby mode entry input active
low.
Caution: External pull-up to V
normal mode.
Output: Standby mode active low output following
Software Standby mode entry.
Note: In Standby mode all pins are in high
impedance except those marked Active in Stdby.
Stabilization for low power voltage regulator.
Requires external capacitors of at least 1µF
between V
Note: If the low power voltage regulator is
bypassed, this pin can be connected to an external
1.8V supply.
Stabilization for main voltage regulator. Requires
external capacitors of at least 10µF + 33nF
between V
Stabilization for main voltage regulator.
Supply voltage for A/D Converter
Ground voltage for A/D Converter
Port 1.0
Port 1.1
Port 1.2
Port 1.3
Port 1.4
function
reset)
(after
Main
18BKP
18
Timer 3: Output
Compare B
Timer 3: Input
Capture A or
External Clock
input
Timer 3: Output
Compare A
Timer 3: Input
Capture B
Timer 1: Input
Capture A
and V
and V
SS18
Alternate function
SS18BKP
. See
System architecture
ADC: Analog input 0
ADC: Analog input 1
ADC: Analog input 2
ADC: Analog input 3
Timer 1: External
Clock input
Figure
33
. See
required to select
Figure
5.
5.
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