AD9518-3/PCBZ Analog Devices Inc, AD9518-3/PCBZ Datasheet - Page 61
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AD9518-3/PCBZ
Manufacturer Part Number
AD9518-3/PCBZ
Description
BOARD EVAL FOR AD9518-3
Manufacturer
Analog Devices Inc
Specifications of AD9518-3/PCBZ
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
AD9518-3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
APPLICATION NOTES
USING THE AD9518 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR can be expressed approximately by
where:
f
t
Figure 50 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
For more information, see Application Note AN-756, Sampled
Systems and the Effects of Clock Phase Noise and Jitter, and
Application Note AN-501, Aperture Uncertainty and ADC System
Performance, at www.analog.com.
A
J
is the rms jitter on the sampling clock.
is the highest analog frequency being digitized.
110
100
90
80
70
60
50
40
30
SNR
10
(dB)
Figure 50. SNR and ENOB vs. Analog Input Frequency
=
20
×
log
⎛
⎜
⎜
⎝
2
π
1
f
f
A
A
100
t
(MHz)
J
⎞
⎟
⎟
⎠
SNR = 20log
2πf
1
A
t
J
1k
18
16
14
12
10
8
6
Rev. 0 | Page 61 of 64
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9518 features LVPECL outputs that provide differential
clock outputs, which enable clock solutions that maximize
converter SNR performance. The input requirements of the
ADC (differential or single-ended, logic level termination)
should be considered when selecting the best clocking/
converter solution.
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9518 provide the lowest jitter
clock signals available from the AD9518. The LVPECL outputs
(because they are open-emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 41 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
is recommended, as shown in Figure 51. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the switching threshold (V
VS_LVPECL
VS_LVPECL
LVPECL
LVPECL
200Ω
Figure 52. LVPECL with Parallel Transmission Line
Figure 51. LVPECL Far-End Thevenin Termination
0.1nF
0.1nF
V
(NOT COUPLED)
200Ω
SINGLE-ENDED
T
= V
S
TRANSMISSION LINE
100Ω DIFFERENTIAL
50Ω
50Ω
– 1.3V
S
− 1.3 V).
(COUPLED)
127Ω
83Ω
VS_LVPECL
100Ω
127Ω
83Ω
VS_LVPECL
LVPECL
V
AD9518-3
S
LVPECL