EVAL-AD7693CB Analog Devices Inc, EVAL-AD7693CB Datasheet - Page 20

• Manufacturer Part Number: EVAL-AD7693CB
• Description: BOARD EVAL FOR AD7693 ADC
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7693CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 18mW @ 500kSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7693
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7693
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host with an interrupt input and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.
The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
ACQUISITION
SDO
CNV
SCK
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
Figure 41. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Figure 40. CS Mode, 4-Wire with Busy Indicator Connection Diagram
t
EN
SDI
AD7693
CNV
SCK
1
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t
t
HSDO
DSDO
SDO
D15
2
VIO
t
CYC
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7693
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17
or when SDI goes high (whichever occurs first), SDO returns to
high impedance.
D14
3
ACQUISITION
CS1
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
t
ACQ
t
SCKL
t
SCKH
15
t
SCK
16
D1
17
D0
t
DIS
th
SCK falling edge,