EVAL-AD7661CB Analog Devices Inc, EVAL-AD7661CB Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD7661CB
• Description: BOARD EVAL FOR AD7661
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7661CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 16mW @ 100kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7661
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CONVERSION CONTROL
Figure 33 shows the detailed timing diagrams of the conversion
process. The AD7661 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD .
Conversions can be automatically initiated with the AD7661. If
CNVST is held LOW when BUSY is LOW, the AD7661 controls
the acquisition phase and automatically initiates a new
conversion. By keeping CNVST LOW, the AD7661 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7661 can run slightly
faster than the guaranteed 100 kSPS.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (i.e., 50 Ω) termination should be added
close to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock CNVST with a
high frequency, low jitter clock, as shown in Figure 26.
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CS = RD = 0
MODE
CNVST
CNVST
BUSY
RESET
CNVST
BUSY
BUSY
DATA
DATA
BUS
Figure 35. Master Parallel Data Timing for Reading (Continuous Read)
ACQUIRE
t
t
3
5
t
3
t
Figure 33. Basic Conversion Timing
PREVIOUS CONVERSION DATA
CONVERT
1
t
7
Figure 34. RESET Timing
t
4
t
t
1
9
t
2
t
6
t
10
ACQUIRE
t
t
4
8
t
8
t
11
AD7661
NEW DATA
CONVERT