EVAL-AD7896CB Analog Devices Inc, EVAL-AD7896CB Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD7896CB
• Description: BOARD EVAL FOR AD7896
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7896CB

• Rohs Status: RoHS non-compliant
• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ 5.5 V
• Power (typ) @ Conditions: 9mW @ 100kSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7896

Parameter
t
t
t
t
t
t
NOTES
1
2
3
4
Parameter
POWER REQUIREMENTS
NOTES
1
2
3
4
5
Specifications subject to change without notice.
TIMING CHARACTERISTICS
REV. C
The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t
1
2
3
4
5
6
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V
processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See Serial Interface section for more information.
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2 V.
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
of the part and as such is independent of external bus loading capacitances.
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; J Version: 0°C to +70°C; S Version: –55°C to +125°C.
Applies to Mode 1 operation. See the section on Operating Modes.
See Terminology.
Sample tested @ 25°C to ensure compliance.
This 14 µs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge
of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the wake-up time plus conversion time, hence 14 µs. This can be seen from Figure 3.
Note that if the CONVST pulsewidth is greater than 6 µs, the effective conversion time will increase beyond 14 µs.
V
I
Power Dissipation
Power-Down Mode
DD
DD
I
T
I
T
Power Dissipation @ 25°C
DD
DD
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
MIN
MIN
@ 25°C
@ 25°C
to T
to T
OUTPUT
MAX
MAX
A, B Versions
40
40
40
60
100
10
50
2
2
3
4
PIN
TO
3
50pF
J Version
40
40
40
60
100
10
50
2
2
3
4
A Version
2.7/5.5
4
5
5
15
50
150
13.5
10.8
3
1.6mA
400 A
1
(V
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V)
1.6V
1
S Version
40
45
45
70
110
10
50
2
2
3
4
B Version
2.7/5.5
4
5
10.8
5
15
50
150
13.5
3
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
–3–
J Version
2.7/5.5
4
5
10.8
5 typ
75
50
500
13.5
Test Conditions/Comments
CONVST Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
Data Access Time after Falling Edge of SCLK
V
V
Data Hold Time after Falling Edge of SCLK
Bus Relinquish Time after Falling Edge of SCLK
6
DD
DD
, quoted in the timing characteristics is the true bus relinquish time
S Version Unit
2.7/5.5
4
5
10.8
5
75
50
500
13.5
= 5 V ± 10%
= 2.7 V to 3.6 V
DD
V min/max
mA max
mA max
mW max
µA max
µA max
µA max
µA max
µW max
) and timed from a voltage level of 1.4 V.
4
, and the setup time required for the user’s
Test Conditions/
V
V
V
Digital Inputs @ DGND
V
V
V
V
V
Comments
Digital Input @ DGND,
Digital Inputs @ DGND,
DD
DD
DD
DD
DD
DD
DD
DD
= 2.7 V to 3.6 V
= 5 V ± 10%
= 2.7 V, Typically 9 mW
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
= 5 V ± 10%
= 5 V ± 10%
= 2.7 V
AD7896