EVAL-AD7664CB Analog Devices Inc, EVAL-AD7664CB Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD7664CB
• Description: BOARD EVAL FOR AD7664
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7664CB

• Rohs Status: RoHS non-compliant
• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 570k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 115mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7664
• Lead Free Status / Rohs Status: Not Compliant

REV. E
Pin No.
1
2
3, 40–42,
44–48
4
5
6
7
8
9–12
13
14
15
D[0:3]
Mnemonic
AGND
AVDD
NC
DGND
OB/2C
WARP
IMPULSE
SER/PAR
D4
or EXT/INT
D5
or INVSYNC
D6
or INVSCLK
Type
P
P
DI
DI
DI
DI
DI
DO
DI/O
DI/O
DI/O
NC = NO CONNECT
Description
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
No Connect.
Must Be Tied to the Ground Where DVDD Is Referred.
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a twos complement output from
its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In
this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless
of the state of SER/PAR.
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state
of the SYNC signal. It is active in both Master and Slave Mode. When LOW, SYNC is active
HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both Master and Slave Mode.
IMPULSE
SER/PAR
OB/2C
WARP
AGND
DGND
AVDD
NC
PIN FUNCTION DESCRIPTIONS
D0
D1
D2
D3
10
11
12
1
2
3
4
5
6
7
8
9
PIN CONFIGURATION
48 47 46 45 44
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
IDENTIFIER
(Not to Scale)
TOP VIEW
–5–
AD7664
43 42 41 40
39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
AD7664