EVAL-AD1953EB Analog Devices Inc, EVAL-AD1953EB Datasheet - Page 2

• Manufacturer Part Number: EVAL-AD1953EB
• Description: BOARD EVAL FOR AD1953
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1953EB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EVAL-AD1953EB
PERFORMANCE SPECIFICATIONS
The typical evaluation board performance is tabulated below.
1. SNR
2. DR, A-Weighted
3. THD + N
4. Frequency Response
5. Noise Floor
6. Full-Scale Audio Output 2.0 V
FUNCTIONAL DESCRIPTION
The AD1953 evaluation board presents a reference design that
can be used as a suggested layout and circuit implementation
that will deliver optimal performance from the SigmaDSP audio
processor. As far as is possible, current assembly methods and
components are used on the evaluation board. Most components
are surface-mount devices, although there is a version of the
evaluation board that uses through-hole components in the
output filters, and a four-layer printed circuit board is used with
full internal power and ground planes for superior noise perfor-
mance. A schematic, bill of materials, and PCB plots are
included for guidance.
POWER SUPPLIES
The board is divided into analog and digital sections, with common
power supplies.
The power supply is input via binding posts J8, J9, and J10. The
recommended supply settings are +12 V dc with a maximum
current of +350 mA and –12 V dc with a maximum current of
–50 mA. An on-board, low noise voltage regulator (U11) provides
5 V dc, ± 5% to the evaluation board circuit.
DIGITAL SIGNAL INPUTS AND OUTPUTS
RCA phone jack J1 and optical TOSLINK input U1 may be used
for standard consumer mode S/PDIF input signals. J1 is terminated
with a 75 Ω resistor. Switch S1 selects between J1 and U1 inputs
and feeds the selected signal to the digital interface receiver (U2).
The EXT DATA INTF 1/2/3 (J14, J15, and J16) inputs permit
access, buffered via U13, to the BCLK, LRCLK, SDATA, and
MCLK inputs of the AD1953. This permits testing with left-
justified, I
SW3 must be set to correspond to the input data format. When
using the direct input header, it is necessary to provide all four
signals: MCLK, BCLK, LRCLK, and SDATA. A termination
network consisting of a series-connected 100 Ω resistor and a 47 pF
capacitor is shunted across each signal line to reduce line reflections.
Digital audio signals are output through the RCA phone jack J2
or TOSLINK output U5. Both output jacks are always “on,” so
no switch is needed to select between the two. The transformer
(U6) on the output buffers the external connection from the rest
of the evaluation board to prevent a ground loop.
Header J13 is for the serial data output from the input MUX
and the data capture serial output. Either of these two signals,
coupled with the left/right clock and bit clock signals, form a
valid 3-wire output. This header can be used to connect an external
DAC to the AD1953 evaluation board.
Twenty-lead header J17 is for interfacing to an Analog Devices
codec evaluation board. This connection can be used to supply
two serial data lines from external ADCs and all of the neces-
2
S, or right-justified serial input modes. Note that switch
112 dB ± 1 dB
112 dB ± 1 dB
–100 dB ± 2 dB
±0.2 dB, 20 Hz to 20 kHz (0 dBFS)
–145 dB
rms
–2–
sary clocks to the AD1953 evaluation board, as well as to send
the serial data to the external DACs.
Headers J6 and J7 are for future expansion and functionality of
the evaluation board.
EXTERNAL SPI CONTROL PORT
The AD1953 evaluation board includes a 25-lead header that
interfaces the chip’s SPI input with a computer’s parallel port.
This port is capable of full read/write operation for all of the memories
(program and parameter) and some of the SPI registers. Most
signal processing parameters are controlled by writing new values
to the parameter RAM using the SPI port. Other functions, such
as volume and de-emphasis filtering, are programmed by writing
to SPI control registers. Details of signal format and timing can
be found in the AD1953 data sheet.
AUDIO SIGNAL OUTPUTS
RCA jacks J3, J4, and J5 provide left, right, and sub outputs,
respectively. The output is low-pass filtered with an anti-image
filter and converted from a differential voltage output to single-
ended voltage by op amps U8 and U9. The left and right channel
filters’ –3 dB cutoff frequency is 100 kHz and has an approximate
third order Bessel (linear phase) response. The subwoofer chan-
nel uses the same filter but with a –3 dB cutoff at 10 kHz. The
output impedance is approximately 600 Ω. The full-scale output
signal is 2.0 V
SWITCH AND JUMPER FUNCTIONS
A quick reference for the default switch and jumper positions is
shown in Table I. These settings should be used for a first-time
use of the evaluation board. All directional references assume that
the board is facing with the digital connections on the left and the
analog connections on the right. A more detailed description of
each switch and jumper follows.
Jumper/Switch Position
S1
S2
S4
S5
SW2
SW3
LK2
LK5
LK6
LK9
LK10
LK11
Slide switch S1 selects between the RCA S/PDIF input and the
TOSLINK input.
Push-button switch SW1 provides a RESET function via reset
generator U12 (ADM811) and a “clean” 240 ms delay after release.
U12 also provides a 240 ms reset pulse at power-up.
A 16-position rotary switch (SW2) controls the signal routing on
the evaluation board. The source of the SDATA, BCLK, and
LRCLK signals for each of the three MUXes is indicated in Table II.
Table III shows the source of signals driving the CS8404A (U4,
S/PDIF digital output transmitter). In each of these two tables,
Table I. Default Switch/Jumper Positions
rms
for all channels.
Down
Right
Don’t Care
Don’t Care
0
0
B (Right)
On (Down)
Off (Up)
C (Bottom)
B (Right)
B (Right)
Setting
RCA Input
Mute Off
For Future Functionality
For Future Functionality
See Tables II and III
See Table IV
5 V
AVDD Reference
XREF Off
DIR_MCLK
MCLK1_INTF
MCLK2_INTF
REV. 0