R0E0200F2EMU00 Renesas Electronics America, R0E0200F2EMU00 Datasheet - Page 65

• Manufacturer Part Number: R0E0200F2EMU00
• Description: EMULATOR E200F FOR SH7780 SRS
• Manufacturer: Renesas Electronics America
• Series: SuperH®r
• Type: In-Circuit Emulatorr

Specifications of R0E0200F2EMU00

• Contents: Emulator Board, Cables, Software and Documentation
• For Use With/related Products: SH7780
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6. If a completion-type exception occurs during exception branch acquisition, the next address to
7. The AUD trace is disabled while the profiling function is used.
8. If breaks occur immediately after executing non-delayed branch and TRAPA instructions and
9. For the result by software trace, a value in the [Data] item is not correct (that value is correct
3.2.3
1. Set the JTAG clock (TCK) frequency to lower than the frequency of the peripheral module
2. The initial value of the JTAG clock (TCK) is 1.25 MHz.
3. A value to be set for the JTAG clock (TCK) is initialized after executing [Reset CPU] or
4. Set the AUD clock (AUDCK) frequency to 50 MHz or lower. If the frequency is higher than
3.2.4
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.
3. During step operation, the specified BREAKPOINT and Event Condition breaks are disabled.
4. When execution resumes from the address where a BREAKPOINT is specified and a break
5. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
the address in which an exception occurs is acquired.
generating a branch due to exception or interrupt, a trace for one branch will not be acquired
immediately before such breaks.
However, this does not affect on generation of breaks caused by a BREAKPOINT and a break
before executing instructions of Event Condition.
for window trace).
clock.
[Reset Go]. Thus the TCK value will be 1.25 MHz.
50 MHz, the emulator will not operate normally.
It cannot be set to the following addresses:
• An area other than CS and the internal RAM
• An instruction in which Event Condition 2 is satisfied
• A slot instruction of a delayed branch instruction
occurs before the Event Condition execution, single-step operation is performed at the address
before execution resumes. Therefore, realtime operation cannot be performed.
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
Notes on Using the JTAG (H-UDI) Clock (TCK) and AUD Clock (AUDCK)
Notes on Setting the [Breakpoint] Dialog Box
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