R0E0200F2EMU00 Renesas Electronics America, R0E0200F2EMU00 Datasheet - Page 57

• Manufacturer Part Number: R0E0200F2EMU00
• Description: EMULATOR E200F FOR SH7780 SRS
• Manufacturer: Renesas Electronics America
• Series: SuperH®r
• Type: In-Circuit Emulatorr

Specifications of R0E0200F2EMU00

• Contents: Emulator Board, Cables, Software and Documentation
• For Use With/related Products: SH7780
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

When point-to-point and trace acquisition condition are set simultaneously, they are ANDed.
Notes on Internal Trace:
• Timestamp
Table 3.11 Timing for the Timestamp Acquisition
Item
M-bus data access
Branch
I-bus
• Point-to-point
• Halting a trace
Set the address condition as H’2000 in the [Event Condition 5] dialog box.
Set [I-Trace] as [Ch4 to Ch5 PtoP] in the [Combination action (Sequential or PtoP)] dialog box.
The timestamp is the clock counts of Bφ (48-bit counter). Table 3.11 shows the timing for
acquiring the timestamp.
The trace-start condition is satisfied when the specified instruction has been fetched.
Accordingly, if the trace-start condition has been set for the overrun-fetched instruction (an
instruction that is not executed although it has been fetched at a branch or transition to an
interrupt), tracing is started during overrun-fetching of the instruction. However, when
overrun-fetching is achieved (a branch is completed), tracing is automatically suspended.
If the start and end conditions are satisfied closely, trace information will not be acquired
correctly.
The execution cycle of the instruction fetched before the start condition is satisfied may be
traced.
When the I-bus is acquired, do not specify point-to-point.
Memory access may not be acquired by the internal trace if it occurs at several instructions
immediately before satisfaction of the point-to-point end condition.
Do not set the trace-end condition for the SLEEP instruction and the branch instruction that the
delay slot becomes the SLEEP instruction.
Acquisition Information
Fetch
Data access
Counter value when data access (read or write) has
been completed
completed after a branch
Counter value when a fetch has been completed
Counter value when data access has been completed
Counter Value Stored in the Trace Memory
Counter value when the next bus cycle has been
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