M3062PT3-CPE-4 Renesas Electronics America, M3062PT3-CPE-4 Datasheet - Page 71

• Manufacturer Part Number: M3062PT3-CPE-4
• Description: DEV COMPACT EMULATOR M16C/26A,28
• Manufacturer: Renesas Electronics America
• Type: In Circuit Debuggerr

Specifications of M3062PT3-CPE-4

• Contents: Compact Emulator, IDE, Assembler and Linker
• For Use With/related Products: M16C/62P
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5. Trace window (source display)
M3062PT3-CPE User’s Manual
3. Trace window (bus display)
4. Trace window (disassemble display)
REJ10J1007-0400 Rev.4.00 July 29, 2009
Explanation of the trace window (bus
display)
The following explains the displayed contents, from left to
right.
- Cycle
- Label
- Address
- Data
- BUS
- BHE
- BIU
- R/W
- RWT
- CPU
Shows trace cycles. Double-click here to bring up a
dialog box to change the displayed cycle.
Shows labels corresponding to address bus information.
Double-click here to bring up a dialog box to search for
addresses.
Shows the status of the address bus.
Shows the status of the data bus.
Shows the width of the external data bus. In the present
emulator, “16b” for 16 bits wide bus and “8b” for 8 bits
wide bus are displayed.
Shows the status (0 or 1) of the BHE (Byte High Enable)
signal. If this signal = 0, the odd-address data is valid.
Shows the status between the BIU (Bus Interface Unit)
and memory or I/O.
Symbol Status
–
DMA
INT
IB
DB
IW
DW
Shows the status of the data bus.
Displayed as “R” for Read, “W” for Write, and “–” for
no access.
This is the signal to indicate a valid bus cycle. When
valid, RWT = 0. The Address, Data, and the BIU signals
are effective when this signal is 0.
Shows the status between the CPU and BIU (Bus
Interface Unit).
Symbol Status
–
CB
RB
QC
CW
RW
3. Usage (How to Use the Emulator Debugger)
Non-active
Data access by other than the CPU, e.g., by
DMA
Interrupt acknowledge cycle start
Instruction code read by the CPU (in bytes)
Data access by the CPU (in bytes)
Instruction code read by the CPU (in words)
Data access by the CPU (in words)
Non-active
Op-code read (in bytes)
Operand read (in bytes)
Instruction queue buffer clear
Op-code read (in words)
Operand read (in words)
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