AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 37
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
8.14
8.15
6438ES–ATARM–21-Jun-10
Debug Unit
Chip Identification
The AT91SAM9G45 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip
ID Extension Register.
• One External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
• Vectoring
• Protect Mode
• Fast Forcing
• Composed of two functions
• Two-pin UART
• Debug Communication Channel Support
• Chip ID: 0x819B05A2
• Ext ID: 0x00000004
• JTAG ID: 05B2_703F
• ARM926 TAP ID: 0x0792603F
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
– Easy debugging by preventing automatic operations when protect modes are
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
– Two-pin UART
– Debug Communication Channel (DCC) support
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
enabled
processor
Generator
the ARM Processor’s ICE Interface
AT91SAM9G45
37