HW-V5-ML507-UNI-G Xilinx Inc, HW-V5-ML507-UNI-G Datasheet - Page 43

• Manufacturer Part Number: HW-V5-ML507-UNI-G
• Description: EVAL PLATFORM V5 FXT
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr
• Type: FPGAr

Specifications of HW-V5-ML507-UNI-G

• Contents: ML507 Platform, DVI adapter, CompactFlash Card and SATA Cross-Over Cable
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VFX70TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ML507
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
40. PCI Express Interface
R
Table 1-25
RocketIO transceivers to the Virtex-5 FPGA integrated Endpoint block for PCIe designs.
See the Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs
more information.
Table 1-25: PCIe Connection to FPGA
Notes:
1. For ML505/ML506 platforms, access is through GTP0 of GTP_X0Y1.
2. For ML507 platforms, access is through GTX0 of GTX_X0Y2.
PCIE_RX_N
PCIE_RX_P
PCIE_TX_N
PCIE_TX_P
PCIE_CLK_N
PCIE_CLK_P
PCIE_PRSNT_B
PCIE_PERST_B
PCIE_WAKE_B
Pin Name
shows the PCIe connector (P21) that provides single-lane access through the
FPGA Pin
AF24
AD2
(U1)
AF1
AE1
AE2
AF3
AF4
-
-
www.xilinx.com
Connector Pin
A1, B17
Edge
(P21)
A17
A16
A14
A13
A11
B15
B14
B11
Integrated Endpoint block receive pair
Integrated Endpoint block transmit pair
Integrated Endpoint block differential
clock pair from PCIe edge connector
Integrated Endpoint block present signal
Integrated Endpoint block reset signal
available on CPLD
Integrated Endpoint block wake signal
available on CPLD
Description
Detailed Description
[Ref 11]
for
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