MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 24

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overall DC Electrical Characteristics
Figure 2
The core voltage must always be provided at nominal 1.0 V or 1.1 V. (See
Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages
shown in
receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM
interface uses differential receivers referenced by the externally supplied MV
appropriate for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS
receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
24
shows the undershoot and overshoot voltages at the interfaces of the MPC8536E.
Table
2. The input voltage threshold scales with respect to the associated I/O supply voltage. OV
V
IH
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
V
Note:
1. t
2. With the PCI overshoot allowed (as specified above), the device
IL
Figure 7. Overshoot/Undershoot Voltage for GV
B/G/L/OV
For I
For DDR, t
For eTSEC, t
For eLBC, t
For PCI, t
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
CLOCK
B/G/L/OV
2
C and JTAG, t
GND – 0.3 V
GND – 0.7 V
B/G/L/OV
refers to the clock period associated with the respective interface:
DD
CLOCK
DD
CLOCK
CLOCK
+ 20%
CLOCK
+ 5%
GND
DD
references PCI1_CLK or SYSCLK.
references MCLK.
references LCLK.
CLOCK
references EC_GTX_CLK125.
references SYSCLK.
Not to Exceed 10%
of t
CLOCK
Table 2
REF
1
n signal (nominally set to GV
for actual recommended core voltage).
DD
/OV
DD
/LV
DD
Freescale Semiconductor
DD
and LV
DD
/2) as is
DD
based